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Ulrich Kühne
Person information
- affiliation: Telecom Paris, Department of Communication and Electronics (COMELEC), France
- affiliation (PhD 2009): University of Bremen, Institute of Computer Architecture, Germany
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2020 – today
- 2022
- [j7]Maxime Ayrault, Ulrich Kühne
, Etienne Borde:
Finding Optimal Moving Target Defense Strategies: A Resilience Booster for Connected Cars. Inf. 13(5): 242 (2022) - 2021
- [j6]Hervé Chabanne
Side channel attacks for architecture extraction of neural networks. CAAI Trans. Intell. Technol. 6(1): 3-16 (2021) - [c42]Hervé Chabanne
Telepathic Headache: Mitigating Cache Side-Channel Attacks on Convolutional Neural Networks. ACNS (1) 2021: 363-392 - [c41]Lars Tebelmann
Analysis and Protection of the Two-Metric Helper Data Scheme. COSADE 2021: 279-302 - [c40]Maxime Ayrault, Etienne Borde, Ulrich Kühne, Jean Leneutre:
Moving Target Defense Strategy in Critical Embedded Systems: A Game-theoretic Approach. PRDC 2021: 27-36 - [c39]Hervé Chabanne, Jean-Luc Danger, Linda Guiga, Ulrich Kühne:
Parasite: Mitigating Physical Side-Channel Attacks Against Neural Networks. SPACE 2021: 148-167 - [i1]Lars Tebelmann, Ulrich Kühne, Jean-Luc Danger, Michael Pehl:
Analysis and Protection of the Two-metric Helper Data Scheme. IACR Cryptol. ePrint Arch. 2021: 830 (2021) - 2020
- [c38]Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert, Baptiste Pecatte:
Processor Anchor to Increase the Robustness Against Fault Injection and Cyber Attacks. COSADE 2020: 254-274
2010 – 2019
- 2019
- [c37]Maxime Ayrault, Etienne Borde, Ulrich Kühne:
Run or Hide? Both! A Method Based on IPv6 Address Switching to Escape While Being Hidden. MTD@CCS 2019: 47-56 - [c36]Jean-Luc Danger, Laurent Fribourg, Ulrich Kühne, Maha Naceur:
LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan Detection. DSD 2019: 269-276 - [e4]Karine Heydemann, Ulrich Kühne, Letitia Li:
Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, PROOFS 2019, colocated with CHES 2018, Atlanta, GA, USA, August 24, 2019. Kalpa Publications in Computing 11, EasyChair 2019 [contents] - 2018
- [j5]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11: 29-45 (2018) - [c35]Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, Abdelmalek Si-Merabet, Michaël Timbert:
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity. DSD 2018: 529-536 - [e3]Lejla Batina, Ulrich Kühne, Nele Mentens:
PROOFS 2018, 7th International Workshop on Security Proofs for Embedded Systems, colocated with CHES 2018, Amsterdam, The Netherlands, September 13, 2018. Kalpa Publications in Computing 7, EasyChair 2018 [contents] - 2017
- [e2]Ulrich Kühne, Jean-Luc Danger, Sylvain Guilley:
PROOFS 2017, 6th International Workshop on Security Proofs for Embedded Systems, Taipei, Taiwan, September 29th, 2017. EPiC Series in Computing 49, EasyChair 2017 [contents] - 2016
- [c34]Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE 2016: 1048-1053 - 2015
- [c33]Judith Peters, Robert Wille
A generic representation of CCSL time constraints for UML/MARTE models. DAC 2015: 122:1-122:6 - [c32]Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. ISVLSI 2015: 1-6 - [c31]Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Ensuring safety and reliability of IP-based system design - A container approach. RSP 2015: 76-82 - [c30]Laurent Fribourg, Ulrich Kühne, Nicolas Markey:
Game-based Synthesis of Distributed Controllers for Sampled Switched Systems. SynCoP 2015: 48-62 - [e1]Rolf Drechsler
Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015. Springer 2015, ISBN 978-3-658-09993-0 [contents] - 2014
- [j4]Laurent Fribourg, Ulrich Kühne, Romain Soulat:
Finite controlled invariants for sampled switched systems. Formal Methods Syst. Des. 45(3): 303-329 (2014) - [c29]Amr A. R. Sayed-Ahmed, Hossam A. H. Fahmy, Ulrich Kühne:
Verification of the decimal floating-point square root operation. ETS 2014: 1-2 - [c28]Christoph Hilken, Julia Seiter, Robert Wille
Verifying consistency between activity diagrams and their corresponding OCL contracts. FDL 2014: 1-7 - [c27]Julia Seiter, Robert Wille
Automatic refinement checking for formal system models. FDL 2014: 1-8 - [c26]Rolf Drechsler
Safe IP Integration Using Container Modules. ISED 2014: 1-4 - [c25]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Behaviour Driven Development for Tests and Verification. TAP@STAF 2014: 61-77 - 2013
- [j3]Laurent Fribourg, Ulrich Kühne:
Parametric Verification and Test Coverage for Hybrid Automata using the inverse Method. Int. J. Found. Comput. Sci. 24(2): 233-250 (2013) - [c24]Laurent Fribourg, Ulrich Kühne, Romain Soulat:
Constructing Attractors of Nonlinear Dynamical Systems. FSFMA 2013: 53-60 - 2012
- [c23]Étienne André
IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems. FM 2012: 33-36 - [c22]Rolf Drechsler
Completeness-Driven Development. ICGT 2012: 38-50 - 2011
- [c21]Mathias Soeken
Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422 - [c20]Daniel Große
Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI 2011: 223-228 - [c19]Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. ISORC Workshops 2011: 181-188 - [c18]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV 2011: 183-192 - [c17]Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler:
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV 2011: 269-278 - [c16]Laurent Fribourg, Ulrich Kühne:
Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method. RP 2011: 191-204 - 2010
- [j2]Ulrich Kühne, Daniel Große, Rolf Drechsler
Towards Fully Automatic Synthesis of Embedded Software. IEEE Embed. Syst. Lett. 2(3): 53-57 (2010) - [c15]Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow:
Automated formal verification of processors based on architectural models. FMCAD 2010: 129-136
2000 – 2009
- 2009
- [b1]Ulrich Kühne:
Advanced automation in formal verification of processors. University of Bremen, 2009, ISBN 978-3-8322-8619-4, pp. 1-173 - [c14]Ulrich Kühne, Daniel Große
Property analysis and design understanding. DATE 2009: 1246-1249 - [c13]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331 - [c12]Daniel Große
Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176 - [c11]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the Accuracy of SAT-based Debugging. MBMV 2009: 47-56 - [c10]André Sülflow, Ulrich Kühne, Görschwin Fey
WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17 - [c9]Ulrich Kühne, Sven Beyer, Christian Pichler:
Generating an Efficient Instruction Set Simulator from a Complete Property Suite. IEEE International Workshop on Rapid System Prototyping 2009: 109-115 - 2008
- [j1]Daniel Große
Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1305-1314 (2008) - [c8]Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler:
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV 2008: 169-178 - [c7]Ulrich Kühne, Daniel Große
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV 2008: 88-93 - 2007
- [c6]Daniel Große, Ulrich Kühne, Rolf Drechsler:
Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181 - [c5]Ulrich Kühne, Daniel Große, Rolf Drechsler
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170 - 2006
- [c4]Ulrich Kühne, Nicole Drechsler:
Finding Compact BDDs Using Genetic Programming. EvoWorkshops 2006: 308-319 - [c3]Daniel Große, Ulrich Kühne, Rolf Drechsler:
HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48 - 2005
- [c2]Daniel Große, Ulrich Kühne, Rolf Drechsler:
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312 - [c1]Daniel Große
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137
Coauthor Index
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last updated on 2024-08-08 19:12 CEST by the dblp team
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