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John Marty Emmert
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2020 – today
- 2024
- [j9]Manoj Yasaswi Vutukuru
, John Marty Emmert
A Survey of Electromagnetic Radiation Based Hardware Assurance and Reliability Monitoring Methods in Integrated Circuits. IEEE Access 12: 150623-150638 (2024) - [j8]Negin Moghadasi
Research and Development Priorities for Security of Embedded Hardware Devices. IEEE Trans. Engineering Management 71: 2800-2811 (2024) - [c29]Haipeng Li, Mabon Ninan, Boyang Wang, John Marty Emmert:
TinyPower: Side-Channel Attacks with Tiny Neural Networks. HOST 2024: 320-331 - [c28]Mabon Ninan
A Second Look at the Portability of Deep Learning Side-Channel Attacks over EM Traces. RAID 2024: 630-643 - 2023
- [c27]Chongzhou Fang
Gotcha! I Know What You Are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links. CCS 2023: 2024-2037 - [c26]Chenggang Wang, Jimmy Dani, Shane Reilly, Austen Brownfield, Boyang Wang, John Marty Emmert:
TripletPower: Deep-Learning Side-Channel Attacks over Few Traces. HOST 2023: 167-178 - [c25]Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert:
Reverse Engineering of RTL Controllers from Look-Up Table Netlists. ISVLSI 2023: 1-6 - [c24]Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert:
RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. MWSCAS 2023: 511-515 - [c23]Chenggang Wang
Portability of Deep-Learning Side-Channel Attacks against Software Discrepancies. WISEC 2023: 227-238 - [i1]Chongzhou Fang, Ning Miao, Han Wang, Jiacheng Zhou, Tyler Sheaves, John Marty Emmert, Avesta Sasan, Houman Homayoun:
Gotcha! I Know What You are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links. CoRR abs/2305.07209 (2023) - 2022
- [j7]John Marty Emmert
THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2906-2915 (2022) - [c22]Dallas A. Phillips, Pingxiuqi Chen, John Marty Emmert:
Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation. ICCD 2022: 565-571 - [c21]David C. Bowman, John Marty Emmert:
Hardware Trojan Detection Through Multimodal Image Processing and Analysis. iSES 2022: 712-717 - 2021
- [c20]John Marty Emmert, Sara A. VanDewerker:
EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications. MWSCAS 2021: 816-819 - [c19]Aaron Ruen, Abhijeet Barua
Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs. MWSCAS 2021: 820-825 - [c18]Carla Purdy, John Marty Emmert, Rashmi Jha, Ranga Vemuri
Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. MWSCAS 2021: 836-839 - 2020
- [c17]John Marty Emmert, Anvesh Perumalla, Luis Concha:
An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks. MWSCAS 2020: 840-843
2000 – 2009
- 2007
- [j6]John Marty Emmert, Charles E. Stroud, Miron Abramovici:
Online Fault Tolerance for FPGA Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 216-226 (2007) - 2006
- [j5]Jason A. Cheatham, John Marty Emmert, Stanley Baumgart:
A survey of fault tolerant methodologies for FPGAs. ACM Trans. Design Autom. Electr. Syst. 11(2): 501-533 (2006) - 2004
- [j4]Miron Abramovici, Charles E. Stroud, John Marty Emmert:
Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1284-1294 (2004) - 2003
- [j3]John Marty Emmert, Sandeep Lodha, Dinesh Bhatia
On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics 9(1): 75-90 (2003) - [c16]John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. DFT 2003: 303- - [c15]John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani:
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. DFT 2003: 361-368 - 2002
- [c14]Miron Abramovici, Charles E. Stroud, John Marty Emmert:
Using embedded FPGAs for SoC yield improvement. DAC 2002: 713-724 - 2001
- [j2]John Marty Emmert, Dinesh K. Bhatia
Two-dimensional Placement Using Tabu Search. VLSI Design 12(1): 13-23 (2001) - [c13]John Marty Emmert, Jason A. Cheatham:
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . DFT 2001: 149- - [c12]John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici:
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT 2001: 445-454 - [c11]Miron Abramovici, John Marty Emmert, Charles E. Stroud:
Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. Evolvable Hardware 2001: 73-92 - [c10]Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert:
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. IOLTW 2001: 27-33 - 2000
- [j1]John Marty Emmert, Dinesh K. Bhatia
A Fault Tolerant Technique for FPGAs. J. Electron. Test. 16(6): 591-606 (2000) - [c9]John Marty Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici:
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. FCCM 2000: 165-174 - [c8]John Marty Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici:
Performance Penalty for Fault Tolerance in Roving STARs. FPL 2000: 545-554 - [c7]Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John Marty Emmert:
Improving On-Line BIST-Based Diagnosis for Roving STARs. IOLTW 2000: 31-39 - [c6]Charles E. Stroud, John Marty Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic:
Bridging fault extraction from physical design data for manufacturing test development. ITC 2000: 760-769
1990 – 1999
- 1999
- [c5]John Marty Emmert, Dinesh Bhatia:
A Methodology for Fast FPGA Floorplanning. FPGA 1999: 47-56 - [c4]John Marty Emmert, Dinesh Bhatia
Tabu Search: Ultra-Fast Placement for FPGAs. FPL 1999: 81-90 - [c3]John Marty Emmert, Dinesh Bhatia:
Fast timing driven placement using tabu search. ISCAS (1) 1999: 302-305 - 1998
- [c2]John Marty Emmert, Akash Randhar, Dinesh Bhatia
Fast Floorplanning for FPGAs. FPL 1998: 129-138 - 1997
- [c1]John Marty Emmert, Dinesh Bhatia
Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL 1997: 141-150
Coauthor Index
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last updated on 2024-11-07 20:30 CET by the dblp team
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