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José Luis Rosselló
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2010 – 2019
- 2018
- [j16]Antoni Morro, Vicent Canals, Antoni Oliver
, Miquel L. Alomar, Fabio Galán-Prado, Pedro J. Ballester
A Stochastic Spiking Neural Network for Virtual Screening. IEEE Trans. Neural Networks Learn. Syst. 29(4): 1371-1375 (2018) - 2016
- [j15]Joan Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. Commun. Nonlinear Sci. Numer. Simul. 30(Issues): 316-327 (2016) - 2015
- [j14]Miquel L. Alomar, Miguel C. Soriano
Digital Implementation of a Single Dynamical Node Reservoir Computer. IEEE Trans. Circuits Syst. II Express Briefs 62-II(10): 977-981 (2015) - [c21]Miquel L. Alomar, Vincent Canals, Víctor Martínez-Moll, José Luis Rosselló:
Stochastic-Based Implementation of Reservoir Computers. IWANN (2) 2015: 185-196 - 2014
- [j13]José Luis Rosselló, Vicent Canals
Studying the Role of Synchronized and Chaotic Spiking Neural Ensembles in Neural Information Processing. Int. J. Neural Syst. 24(5) (2014) - [c20]José Luis Rosselló, Vicent Canals, Antoni Oliver
Stochastic Spiking Neural Networks at the EDGE of CHAOS. IJCNN 2014: 2399-2406 - [c19]Miquel L. Alomar, Vicent Canals, Víctor Martínez-Moll, José Luis Rosselló:
Low-cost hardware implementation of Reservoir Computers. PATMOS 2014: 1-5 - 2012
- [j12]José Luis Rosselló, Vincent Canals
Hardware Implementation of Stochastic Spiking Neural Networks. Int. J. Neural Syst. 22(4) (2012) - [c18]José Luis Rosselló, Vincent Canals, Antoni Morro:
Probabilistic-based neural network implementation. IJCNN 2012: 1-7 - [i3]Vincent Canals, Antoni Morro, José Luis Rosselló:
Stochastic-Based Pattern Recognition Analysis. CoRR abs/1202.4495 (2012) - 2010
- [j11]Vincent Canals
Stochastic-based pattern-recognition analysis. Pattern Recognit. Lett. 31(15): 2353-2356 (2010) - [j10]Gabriel Torrens
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 280-284 (2010) - [c17]José Luis Rosselló, Vincent Canals, Antoni Morro:
Hardware implementation of stochastic-based Neural Networks. IJCNN 2010: 1-4
2000 – 2009
- 2009
- [j9]José Luis Rosselló, Vincent Canals, Antoni Morro, Jaume Verd
Chaos-Based Mixed Signal Implementation of Spiking Neurons. Int. J. Neural Syst. 19(6): 465-471 (2009) - [c16]José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro:
Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. ICANN (1) 2009: 421-428 - [c15]José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl:
Practical Hardware Implementation of Self-configuring Neural Networks. ISNN (3) 2009: 1154-1159 - 2008
- [j8]José Luis Rosselló, Ivan de Paúl, Vincent Canals
Self-configuring spiking neural networks. IEICE Electron. Express 5(22): 921-926 (2008) - [j7]José Luis Rosselló, Vincent Canals
A simple CMOS chaotic integrated circuit. IEICE Electron. Express 5(24): 1042-1048 (2008) - [c14]José Luis Rosselló, Vincent Canals
Using stochastic logic for efficient pattern recognition analysis. IJCNN 2008: 1057-1061 - 2007
- [c13]José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura:
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE 2007: 1271-1276 - [i2]Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura:
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. CoRR abs/0710.4733 (2007) - [i1]José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura:
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. CoRR abs/0710.4759 (2007) - 2006
- [j6]Sebastià A. Bota, José Luis Rosselló, Carol de Benito
Impact of Thermal Gradients on Clock Skew and Testing. IEEE Des. Test Comput. 23(5): 414-424 (2006) - [c12]José Luis Rosselló, Jaume Segura
A compact model to identify delay faults due to crosstalk. DATE 2006: 902-906 - [c11]José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN 2006: 659-663 - [c10]José Luis Rosselló, Carol de Benito
Leakage Power Characterization Considering Process Variations. PATMOS 2006: 66-74 - [c9]Sebastià A. Bota
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS 2006: 358-363 - 2005
- [j5]José Luis Rosselló, Carol de Benito
A compact gate-level energy and delay model of dynamic CMOS gates. IEEE Trans. Circuits Syst. II Express Briefs 52-II(10): 685-689 (2005) - [c8]José Luis Rosselló, Vicent Canals
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE 2005: 206-211 - [c7]Sebastià A. Bota
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE 2005: 464-465 - [c6]José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Compact Static Power Model of Complex CMOS Gates. PATMOS 2005: 348-354 - 2004
- [j4]José Luis Rosselló, Jaume A. Segura
An analytical charge-based compact delay model for submicrometer CMOS inverters. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(7): 1301-1311 (2004) - [c5]José Luis Rosselló, Jaume Segura:
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE 2004: 954-961 - [c4]Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi:
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC 2004: 1276-1284 - 2003
- [j3]Josep Altet
Structural RFIC device testing through built-in thermal monitoring. IEEE Commun. Mag. 41(9): 98-104 (2003) - [c3]José Luis Rosselló, Jaume Segura
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS 2003: 51-59 - 2002
- [j2]José Luis Rosselló, Jaume Segura
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 433-448 (2002) - [c2]José Luis Rosselló, Jaume Segura
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS 2002: 219-228 - 2001
- [c1]José Luis Rosselló, Jaume Segura:
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD 2001: 494-
1990 – 1999
- 1998
- [j1]Jaume Segura
A variable threshold voltage inverter for CMOS programmable logic circuits. IEEE J. Solid State Circuits 33(8): 1262-1265 (1998)
Coauthor Index
aka: Vincent Canals
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