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Toru Shimizu
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2020 – today
- 2024
- [e1]Takahiro Yabe, Kota Tsubouchi, Toru Shimizu:
Proceedings of the 2nd ACM SIGSPATIAL International Workshop on Human Mobility Prediction Challenge, HuMob2024, Atlanta, GA, USA, 29 October 2024 - 1 November 2024. ACM 2024, ISBN 979-8-4007-1150-3 [contents] - [d2]Takahiro Yabe
, Kota Tsubouchi
YJMob100K: City-Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories. Version 3. Zenodo, 2024 [all versions] - 2023
- [d1]Takahiro Yabe
YJMob100K: City-Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories. Version 2. Zenodo, 2023 [all versions] - [i5]Takahiro Yabe, Kota Tsubouchi, Toru Shimizu
Metropolitan Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories. CoRR abs/2307.03401 (2023) - 2022
- [c33]Toru Shimizu
GEO-BLEU: similarity measure for geospatial sequences. SIGSPATIAL/GIS 2022: 17:1-17:4 - 2021
- [c32]Toru Shimizu
Improving Land Use Classification using Human Mobility-based Hierarchical Place Embeddings. PerCom Workshops 2021: 305-311 - [i4]Toru Shimizu, Kota Tsubouchi, Takahiro Yabe:
GEO-BLEU: Similarity Measure for Geospatial Sequences. CoRR abs/2112.07144 (2021) - 2020
- [c31]Toru Shimizu
Enabling Finer Grained Place Embeddings using Spatial Hierarchy from Human Mobility Trajectories. SIGSPATIAL/GIS 2020: 187-190 - [c30]Kota Tsubouchi
POI Atmosphere Categorization Using Web Search Session Behavior. SIGSPATIAL/GIS 2020: 630-639 - [c29]Takahiro Yabe
Unsupervised Translation via Hierarchical Anchoring: Functional Mapping of Places across Cities. KDD 2020: 2841-2851 - [i3]Toru Shimizu, Takahiro Yabe, Kota Tsubouchi:
Learning Fine Grained Place Embeddings with Spatial Hierarchy from Human Mobility Trajectories. CoRR abs/2002.02058 (2020)
2010 – 2019
- 2019
- [c28]Sosuke Kato, Toru Shimizu, Sumio Fujita, Tetsuya Sakai:
Unsupervised Answer Retrieval with Data Fusion for Community Question Answering. AIRS 2019: 10-21 - [c27]Takahiro Yabe
City2City: Translating Place Representations across Cities. SIGSPATIAL/GIS 2019: 412-415 - [c26]Takahiro Yabe
Predicting Evacuation Decisions using Representations of Individuals' Pre-Disaster Web Search Behavior. KDD 2019: 2707-2717 - [i2]Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri:
Predicting Evacuation Decisions using Representations of Individuals' Pre-Disaster Web Search Behavior. CoRR abs/1906.07770 (2019) - [i1]Takahiro Yabe, Kota Tsubouchi, Toru Shimizu, Yoshihide Sekimoto, Satish V. Ukkusuri:
City2City: Translating Place Representations across Cities. CoRR abs/1911.12143 (2019) - 2018
- [j15]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. IEICE Trans. Electron. 101-C(7): 488-492 (2018) - [c25]Toru Shimizu
Pretraining Sentiment Classifiers with Unlabeled Dialog Data. ACL (2) 2018: 764-770 - [c24]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. ISCAS 2018: 1-4 - 2017
- [j14]Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. IEICE Trans. Inf. Syst. 100-D(10): 2493-2504 (2017) - [c23]Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Wireless power transfer to stacked modules for IoT sensor nodes. ISOCC 2017: 59-60 - [c22]Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda:
Convolutional neural network for industrial egg classification. ISOCC 2017: 67-68 - [c21]Toru Shimizu:
YJTI at the NTCIR-13 STC Japanese Subtask. NTCIR 2017 - 2016
- [c20]Ryota Shimizu, Shusuke Yanagawa, Yasutaka Monde, Hiroki Yamagishi, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Deep learning application trial to lung cancer diagnosis for medical sensor systems. ISOCC 2016: 191-192 - [c19]Takashi Nakada, Hiroshi Nakamura
Normally-off power management for sensor nodes of global navigation satellite system. ISOCC 2016: 193-194 - [c18]Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. VLSI-SoC 2016: 1-7 - 2014
- [j13]Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9(4): 419-428 (2014) - [c17]Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu:
Normally-off MCU architecture for low-power sensor node. ASP-DAC 2014: 12-16 - [c16]Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara:
What is a good way to expand a silicon value to a solution value? A-SSCC 2014: 389-394 - [c15]Ryota Yasudo
A low power NoC router using the marching memory through type. COOL Chips 2014: 1-3 - [c14]Ryota Yasudo
Design of a low power NoC router using Marching Memory Through type. NOCS 2014: 111-118 - [c13]Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA 2014: 1-6 - 2013
- [j12]Murray Shanahan, Verner P. Bingman, Toru Shimizu, Martin Wild, Onur Güntürkün
Large-scale network organization in the avian forebrain: a connectivity matrix and theoretical analysis. Frontiers Comput. Neurosci. 7: 89 (2013) - [j11]Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toru Shimizu:
On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. IEICE Trans. Electron. 96-C(11): 1420-1427 (2013) - [j10]Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. IEEE J. Solid State Circuits 48(8): 1933-1942 (2013) - 2012
- [c12]Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu:
A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. CICC 2012: 1-4 - 2011
- [j9]Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo:
Low Power Platform for Embedded Processor LSIs. IEICE Trans. Electron. 94-C(4): 394-400 (2011) - [c11]Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu:
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. A-SSCC 2011: 21-24
2000 – 2009
- 2009
- [j8]Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu:
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. IEEE J. Solid State Circuits 44(8): 2251-2259 (2009) - 2008
- [c10]Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu:
Heterogeneous multicore SoC for secure multimedia applications. CICC 2008: 675-678 - 2007
- [j7]Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu:
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Trans. Electron. 90-C(4): 657-665 (2007) - [j6]Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu:
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(1): 183-192 (2007) - [c9]Toru Shimizu, Ram Krishnamurthy:
SE4 Automotive Signal Processing Technologies. ISSCC 2007: 148-149 - 2006
- [j5]Toru Shimizu, Masami Nakajima, Masahiro Kainaga:
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture. IEICE Trans. Electron. 89-C(11): 1512-1518 (2006) - [c8]Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu:
A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC 2006: 1616-1625 - [c7]Kunihiro Yamada, Takashi Furumura, Yasuhiro Seno, Yukihisa Naoe, Kenichi Kitazawa, Toru Shimizu, Koji Yoshida, Masanori Kojima, Hiroshi Mineno, Tadanori Mizuno:
Home-Network of a Mutual Complement Communication System by Wired and Wireless. KES (3) 2006: 189-196 - [c6]Toru Shimizu, Masakazu Ikezaki, Toyohide Watanabe, Taketoshi Ushiama:
Spatial Relation for Geometrical / Topological Map Retrieval. KES (2) 2006: 1224-1231 - 2005
- [j4]Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, Toru Shimizu:
Implementation of Face Recognition Processing Using an Embedded Processor. J. Robotics Mechatronics 17(4): 428-436 (2005) - [c5]Kunihiro Yamada, Kenichi Kitazawa, Hiroki Takase, Toshihiko Tamura, Yukihisa Naoe, Takashi Furumura, Toru Shimizu, Koji Yoshida, Masanori Kojima, Tadanori Mizuno:
Dual Communication System Using Wired and Wireless Correspondence in Home Network. KES (1) 2005: 438-444 - [c4]Kunihiro Yamada, Takashi Furumura, Yoshio Inoue, Kenichi Kitazawa, Hiroki Takase, Yukihisa Naoe, Toru Shimizu, Yoshihiko Hirata, Hiroshi Mineno, Tadanori Mizuno:
Dual Communication System Using Wired and Wireless with the Routing Consideration. KES (1) 2005: 1051-1056 - 2004
- [j3]Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Teruyuki Itou, Masayuki Satou, Naoto Okumura, Yukari Takata, Hirokazu Takata, Mamoru Sakugawa, Takashi Higuchi, Sugako Ohtani, Kei Sakamoto, Naoshi Ishikawa, Masami Nakajima, Shunichi Iwata, Kiyoshi Hayase, Satoshi Nakano, Sachiko Nakazawa, Kunihiro Yamada, Toru Shimizu:
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. IEEE J. Solid State Circuits 39(1): 184-193 (2004) - [c3]Kunihiro Yamada, Yoshihiko Hirata, Yukihisa Naoe, Takashi Furumura, Yoshio Inoue, Toru Shimizu, Koji Yoshida, Masanori Kojima, Tadanori Mizuno:
Dual Communication System Using Wired and Wireless Correspondence in a Small Space. KES 2004: 898-904 - 2002
- [j2]Kunihiro Yamada, Masanori Kojima, Toru Shimizu, Fumiaki Sato, Tadanori Mizuno:
A new RISC processor architecture for MPEG-2 decoding. IEEE Trans. Consumer Electron. 48(1): 143-150 (2002)
1990 – 1999
- 1998
- [c2]Yasuhiro Nunomura, Toru Shimizu, Kazunori Saitoh, Koji Tsuchihashi:
Multimedia applications of microprocessor with embedded DRAM. ICASSP 1998: 3157-3160 - 1997
- [j1]Yasuhiro Nunomura, Toru Shimizu, Osamu Tomisawa:
M32R/D-integrating DRAM and microprocessor. IEEE Micro 17(6): 40-48 (1997)
1980 – 1989
- 1989
- [c1]Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito:
A 32-bit microprocessor with high performance bit-map manipulation instructions. ICCD 1989: 406-409
Coauthor Index
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