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Thomas Polzer

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2020 – today

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2023
[c17]
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  - conf/educon/SteinerLWP23
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Fabian Steiner, Bernhard Lueger, Bernhard Wallisch, Thomas Polzer:
Automated Evaluation System for Microcontroller Assignments. EDUCON 2023: 1-7

2010 – 2019

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2019
[j5]
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Thomas Polzer, Florian Huemer, Andreas Steininger:
An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. 28(Supplement-1): 1940006:1-1940006:21 (2019)
2018
[j4]
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Thomas Polzer, Florian Huemer, Andreas Steininger:
Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. 80: 91-99 (2018)
[c16]
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Florian Huemer, Thomas Polzer, Andreas Steininger:
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS 2018: 141-146
2017
[j3]
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Thomas Polzer, Andreas Steininger:
A Model for the Metastability Delay of Sequential Elements. J. Circuits Syst. Comput. 26(8): 1740010:1-1740010:22 (2017)
[c15]
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Robert Najvirt, Thomas Polzer, Andreas Steininger:
Measuring Metastability with Free-Running Clocks. ASYNC 2017: 18-24
[c14]
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Matthias Függer, Attila Kinali, Christoph Lenzen, Thomas Polzer:
Metastability-Aware Memory-Efficient Time-to-Digital Converters. ASYNC 2017: 49-56
[c13]
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Thomas Polzer, Florian Huemer, Andreas Steininger:
Measuring metastability using a time-to-digital converter. DDECS 2017: 116-121
2016
[j2]
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Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger:
On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. 25(3): 1640020:1-1640020:25 (2016)
[c12]
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Thomas Polzer, Andreas Steininger:
A general approach for comparing metastable behavior of digital CMOS gates. DDECS 2016: 56-61
2015
[c11]
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Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger:
Containment of Metastable Voltages in FPGAs. DDECS 2015: 197-202
[c10]
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Thomas Polzer, Andreas Steininger:
Measuring the Distribution of Metastable Upsets over Time. DSD 2015: 189-196
[c9]
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Thomas Polzer, Andreas Steininger:
Enhanced Metastability Characterization Based on AC Analysis. DSD 2015: 722-729
2013
[j1]
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  - journals/mam/VeeravalliPSSHSDSZVMH13
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Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek:
An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems 37(8-A): 772-791 (2013)
[c8]
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Thomas Polzer, Andreas Steininger:
An Approach for Efficient Metastability Characterization of FPGAs through the Designer. ASYNC 2013: 174-182
[c7]
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Thomas Polzer, Andreas Steininger:
Digital Late-Transition Metastability Simulation Model. DSD 2013: 121-128
[c6]
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Thomas Polzer, Andreas Steininger:
SET propagation in micropipelines. PATMOS 2013: 126-133
[c5]
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Thomas Polzer, Andreas Steininger:
Metastability characterization for muller C-elements. PATMOS 2013: 164-171
2012
[c4]
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Jakob Lechner, Martin Lampacher, Thomas Polzer:
A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding. ACSD 2012: 122-131
[c3]
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Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid:
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD 2012: 8-17
[c2]
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Thomas Polzer, Andreas Steininger, Jakob Lechner:
Muller C-Element Metastability Containment. PATMOS 2012: 103-112

2000 – 2009

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2009
[c1]
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Thomas Polzer, Thomas Handl, Andreas Steininger:
A Metastability-Free Multi-synchronous Communication Scheme for SoCs. SSS 2009: 578-592

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