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J. V. R. Ravindra
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- affiliation: Vardhaman College of Engineering, Shamshabad, Kacharam, Hyderabad, Telangana, India
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2020 – today
- 2024
- [j10]Yagnesh Challagundla, Badri Narayanan K, Krishna Sai Devatha, Bharathi V. C
, J. V. R. Ravindra:
A Multi-Model Machine Learning Approach for Monitoring Calories Being Burnt During Workouts Using Smart Calorie Tracer. EAI Endorsed Trans. Pervasive Health Technol. 10 (2024) - [j9]Hritwik Ghosh, Pavan Kumar P, Irfan Sadiq Rahat
Exploring Deep Learning Models for Accurate Alzheimer's Disease Classification based on MRI Imaging. EAI Endorsed Trans. Pervasive Health Technol. 10 (2024) - [j8]Hritwik Ghosh, Irfan Sadiq Rahat
Convolutional Neural Networks in Malaria Diagnosis: A Study on Cell Image Classification. EAI Endorsed Trans. Pervasive Health Technol. 10 (2024) - [j7]Irfan Sadiq Rahat
Exploring Deep Learning Models for Accurate Alzheimer's Disease Classification based on MRI Imaging. EAI Endorsed Trans. Pervasive Health Technol. 10 (2024) - [c17]Yagnesh Challagundla, Shreeya Dheera Parvatham, Sachi Nandan Mohanty, J. V. R. Ravindra:
Deep Learning-Driven Surveillance for Intrusion Identification using Proactive Intelligent Video Recognition. AVSS 2024: 1-5 - 2023
- [j6]B. Srikanth
Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique. Wirel. Pers. Commun. 131(1): 251-270 (2023) - [j5]B. Srikanth
Correction to: Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique. Wirel. Pers. Commun. 131(1): 271 (2023) - 2022
- [j4]Sangeeta Singh, J. V. R. Ravindra, B. Rajendra Naik:
Proffering Secure Energy Aware Network-On-Chip (Noc) Using Incremental Cryptogine. Sustain. Comput. Informatics Syst. 35: 100682 (2022) - 2021
- [j3]Lavanya Maddisetti
Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor. Comput. Electr. Eng. 92: 107137 (2021) - 2020
- [j2]B. Srikanth
The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model. Trans. Emerg. Telecommun. Technol. 31(12) (2020)
2010 – 2019
- 2019
- [c16]Lavanya Maddisetti
Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters. NORCAS 2019: 1-6 - [c15]Lavanya Maddisetti
Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers. VLSID 2019: 221-226 - 2018
- [c14]M. Lavanya, J. V. R. Ravindra:
Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters. ICM 2018: 96-99 - [c13]Lavanya Maddisetti
Performance Metrics of Inexact Multipliers Based on Approximate 5: 2 Compressors. ISOCC 2018: 84-85 - 2016
- [c12]Chiranjeevi Sheelam, J. V. R. Ravindra:
A novel and efficient design of golay encoder for ultra deep submicron technologies. ICACCI 2016: 275-280 - [c11]Sangeeta Singh
Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip. ISOCC 2016: 5-6 - 2013
- [c10]Gangadhar Reddy Ramireddy, J. V. R. Ravindra, Harikrishna Kamatham:
Design of Ultra Lowpower Full Adder Using Modified Branch Based Logic Style. EMS 2013: 691-696 - [c9]Narasimha Rao Konijeti, J. V. R. Ravindra, Pandurangaiah Yagateela:
Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology. EMS 2013: 697-700 - [c8]J. V. R. Ravindra, Pandurangaiah Yagateela, L. V. Narasimha Prasad
A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications. UKSim 2013: 798-802
2000 – 2009
- 2008
- [c7]J. V. R. Ravindra, M. B. Srinivas:
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI 2008: 111-114 - 2007
- [j1]J. V. R. Ravindra, M. B. Srinivas:
Delay and Energy Efficient Coding Techniques for Capacitive Interconnects. J. Circuits Syst. Comput. 16(6): 929-942 (2007) - [c6]J. V. R. Ravindra, M. B. Srinivas:
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects. DSD 2007: 325-330 - [c5]J. V. R. Ravindra, M. B. Srinivas:
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs. Nano-Net 2007: 25 - [c4]J. V. R. Ravindra, Srinivas Bala Mandalika:
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. SBCCI 2007: 207-211 - 2006
- [c3]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method. DELTA 2006: 336-339 - [c2]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects. ISCAS 2006 - 2005
- [c1]K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas:
A novel deep submicron low power bus coding technique. Circuits, Signals, and Systems 2005: 154-159
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