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Bart Kienhuis
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2010 – 2019
- 2016
- [c34]Tsvetan Shoshkov, Todor P. Stefanov
, Bart Kienhuis:
Parametrized system level design: Real-time X-Ray image processing case study. ASAP 2016: 196-201 - [c33]Wouter van Teijlingen, Rene van Leuken, Carlo Galuzzi, Bart Kienhuis:
Determining Performance Boundaries on High-Level System Specifications. SCOPES 2016: 90-97 - 2013
- [j11]Luciano Lavagno, Mihai T. Lazarescu
HEAP: A Highly Efficient Adaptive multi-Processor framework. Microprocess. Microsystems 37(8-C): 1050-1062 (2013) - 2012
- [c32]Sven van Haastregt, Bart Kienhuis:
Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations. ASAP 2012: 173-176 - [c31]Luciano Lavagno, Mihai T. Lazarescu
HEAP: A Highly Efficient Adaptive Multi-processor Framework. DSD 2012: 509-516 - [c30]Ana Balevic, Bart Kienhuis:
Scaling Data-Intensive Applications on Heterogeneous Platforms with Accelerators. IPDPS Workshops 2012: 1866-1873 - [c29]Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid:
FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations. MCSoC 2012: 51-58 - 2011
- [j10]Ana Balevic, Bart Kienhuis:
KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks. SIGARCH Comput. Archit. News 39(4): 66-71 (2011) - [c28]Razvan Nane
IP-XACT extensions for Reconfigurable Computing. ASAP 2011: 215-218 - [c27]Sven van Haastregt, Stephen Neuendorffer, Kees A. Vissers, Bart Kienhuis:
High level synthesis for FPGAs applied to a sphere decoder channel preprocessor (abstract only). FPGA 2011: 278 - [c26]Ana Balevic, Bart Kienhuis:
A data parallel view on polyhedral process networks. SCOPES 2011: 38-47 - 2010
- [c25]Sven van Haastregt, Eyal Halm, Bart Kienhuis:
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems. DATE 2010: 1297-1300 - [c24]Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki:
Cool MPSoC programming. DATE 2010: 1488-1493
2000 – 2009
- 2009
- [c23]Sven van Haastregt, Bart Kienhuis:
Automated synthesis of streaming C applications to process networks in hardware. DATE 2009: 890-893 - [c22]Barbara M. Chapman, Bart Kienhuis, Eduard Ayguadé
Introduction. Euro-Par 2009: 837-838 - 2008
- [j9]Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. 3(3): 170-180 (2008) - [c21]Bin Jiang, Ed F. Deprettere, Bart Kienhuis:
Hierarchical run time deadlock detection in process networks. SiPS 2008: 239-244 - 2007
- [j8]Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embed. Comput. Syst. 6(2): 13 (2007) - [j7]Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Trans. Signal Process. 55(6-2): 3126-3138 (2007) - [c20]Sjoerd Meijer, Bart Kienhuis, Alexandru Turjan, Erwin A. de Kock:
Interactive presentation: A process splitting transformation for Kahn process networks. DATE 2007: 1355-1360 - [c19]Sjoerd Meijer, Bart Kienhuis, Johan Walters, David Snuijf:
Automatic partitioning and mapping of stream-based applications onto the Intel IXP Network processor. SCOPES 2007: 23-30 - 2005
- [j6]Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
Solving Out-of-Order Communication in Kahn Process Networks. J. VLSI Signal Process. 40(1): 7-18 (2005) - [c18]Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
Expression Synthesis in Process Networks generated by LAURA. ASAP 2005: 15-21 - [c17]Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
Communication Synthesis in a multiprocessor environment. FPL 2005: 360-365 - 2004
- [c16]Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP 2004: 282-292 - [c15]Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
Translating affine nested-loop programs to process networks. CASES 2004: 220-229 - [c14]Todor P. Stefanov
System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE 2004: 340-345 - [c13]Ingrid Verbauwhede
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. DATE 2004: 988-995 - [c12]Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere:
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL 2004: 690-699 - [c11]Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES 2004: 62-76 - [p1]Ingrid Verbauwhede
Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing. Ultra Low-Power Electronics and Design 2004: 141-155 - 2003
- [j5]Bart Kienhuis, Ed F. Deprettere:
Modeling Stream-Based Applications Using the SBF Model of Computation. J. VLSI Signal Process. 34(3): 291-300 (2003) - [c10]Alexandru Turjan, Bart Kienhuis:
Storage Management in Process Networks using the Lexicographically Maximal Preimage. ASAP 2003: 75-85 - [c9]Claudiu Zissulescu, Todor P. Stefanov
Laura: Leiden Architecture Research and Exploration Tool. FPL 2003: 911-920 - 2002
- [j4]Ed F. Deprettere, Bart Kienhuis, Richard L. Walke:
Preface. Des. Autom. Embed. Syst. 7(4): 303-305 (2002) - [j3]Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere:
Compilation From Matlab to Process Networks Realized in FPGA. Des. Autom. Embed. Syst. 7(4): 385-403 (2002) - [c8]Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP 2002: 17-28 - [c7]Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere:
Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES 2002: 7-12 - [c6]Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers:
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges 2002: 18-37 - [c5]Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis:
Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges 2002: 89-111 - 2000
- [j2]Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis:
Deriving Process Networks from Nested Loop Algorithms. Parallel Process. Lett. 10(2/3): 165-176 (2000) - [c4]Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis:
High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP 2000: 79-91 - [c3]Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere:
Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES 2000: 13-17
1990 – 1999
- 1999
- [j1]Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock:
A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. J. VLSI Signal Process. 22(1): 9-20 (1999) - 1998
- [c2]Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf:
The construction of a retargetable simulator for an architecture template. CODES 1998: 125-129 - 1997
- [c1]Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf:
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP 1997: 338-349
Coauthor Index
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