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Yi-Yu Liu
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2020 – today
- 2024
- [j12]Cheng-Hsien Lin
, Kuan-Ting Chen
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-27 (2024) - 2023
- [j11]Yi-Sian Ciou, An-Jie Shih, Shao-Yun Fang
Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4329-4333 (2023) - [j10]Jun-Sheng Wu
ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design. ACM Trans. Design Autom. Electr. Syst. 28(5): 77:1-77:26 (2023) - 2021
- [j9]Jen-Wei Hsieh
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. IEEE Trans. Computers 70(9): 1498-1510 (2021) - 2020
- [c11]An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu:
Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. ICCAD 2020: 21:1-21:6
2010 – 2019
- 2017
- [j8]Yen-Hao Chen
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 820-832 (2017) - 2016
- [c10]Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE 2016: 79-84 - 2014
- [j7]Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu:
Hybrid LUT and SOP Reconfigurable Architecture. J. Inf. Sci. Eng. 30(1): 65-84 (2014) - [j6]Po-Yang Hsu, Yi-Yu Liu:
Buffer Design and Assignment for Structured ASIC. J. Inf. Sci. Eng. 30(1): 107-124 (2014) - 2013
- [j5]Ting-Wei Hung, Yen-Hao Chen, Yi-Yu Liu:
Memory management for dual-addressing memory architecture. IEICE Electron. Express 10(15): 20130467 (2013) - [j4]Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu:
Routability optimization for crossbar-switch structured ASIC design. ACM Trans. Design Autom. Electr. Syst. 18(3): 39:1-39:28 (2013) - [c9]Yen-Hao Chen, Yi-Yu Liu:
Dual-addressing memory architecture for two-dimensional memory access patterns. DATE 2013: 71-76 - 2010
- [j3]Fu-Wei Chen, Yi-Yu Liu:
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 2046-2050 (2010) - [c8]Hsiang-Yuan Yeh, Yi-Yu Liu, Cheng-Yu Yeh, Von-Wun Soo:
Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search. BIBE 2010: 302-303
2000 – 2009
- 2009
- [c7]Fu-Wei Chen, Yi-Yu Liu:
Performance-driven dual-rail insertion for chip-level pre-fabricated design. DATE 2009: 308-311 - [c6]Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu:
Buffer design and optimization for lut-based structured ASIC design styles. ACM Great Lakes Symposium on VLSI 2009: 377-380 - 2008
- [c5]Fu-Wei Chen, Yi-Yu Liu:
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. DATE 2008: 796-799 - 2007
- [j2]Yi-Yu Liu, TingTing Hwang:
Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1155-1161 (2007) - 2006
- [j1]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang:
Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11(4): 890-915 (2006) - [c4]Yi-Yu Liu, TingTing Hwang:
Crosstalk-aware domino logic synthesis. DATE 2006: 1312-1317 - 2004
- [c3]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang:
Crosstalk Minimization in Logic Synthesis for PLA. DATE 2004: 790-795 - 2001
- [c2]LiYi Lin, Yi-Yu Liu, TingTing Hwang:
A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC 2001: 126-132 - [c1]Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu:
Binary decision diagram with minimum expected path length. DATE 2001: 708-712
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