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Yung Sern Tan
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2010 – 2019
- 2016
- [c8]Bai Song Samuel Lee, Yung Sern Tan, Bharatha Kumar Thangarasu, Kiat Seng Yeo, Zhichao Li, Xiaopeng Yu:
An inductorless transimpedance amplifier design for 10 Gb/s optical communication using 0.18-µm CMOS. ISIC 2016: 1-4 - 2013
- [c7]Anh-Tuan Do, Yung Sern Tan, Gordon M. Xiong, Cleo Choong, Zhi-Hui Kong, Kiat Seng Yeo
:
A current-mode stimulator circuit with two-step charge balancing background calibration. ISCAS 2013: 409-412 - [c6]Whye Seng Chong, Yung Sern Tan, Kiat Seng Yeo:
A low power wideband differential transimpedance amplifier for optical receivers in 0.18-μm CMOS. NEWCAS 2013: 1-4 - 2012
- [j1]Yung Sern Tan, Kiat Seng Yeo
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1156-1167 (2012) - [c5]Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo
A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems. APCCAS 2012: 1-4 - [c4]Xiaodan Zou, Lei Liu, Yung Sern Tan, Minkyu Je, Kiat Seng Yeo
Integrated circuits design for neural recording sensor interface. APCCAS 2012: 17-20 - [c3]Haitao Wang, Kiat Seng Yeo, Anh-Tuan Do, Yung Sern Tan, Kai Kang, Zhenghao Lu:
A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor. ISOCC 2012: 383-386 - [c2]Anh-Tuan Do, Yung Sern Tan, Chun Kit Lam, Minkyu Je, Kiat Seng Yeo
Low power implantable neural recording front-end. ISOCC 2012: 387-390 - [c1]Anh-Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. NEWCAS 2012: 525-528
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