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Yizhe Hu
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2020 – today
- 2023
- [j10]Xi Chen
, Yizhe Hu
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits 58(7): 1945-1958 (2023) - [c8]Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu:
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j9]Jianglin Du
A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. IEEE J. Solid State Circuits 57(2): 452-464 (2022) - [j8]Yizhe Hu
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits 57(2): 518-534 (2022) - [j7]Xi Chen
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 973-984 (2022) - [j6]Yizhe Hu
Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3030-3036 (2022) - 2021
- [j5]Jianglin Du
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits 56(11): 3445-3457 (2021) - [j4]Yizhe Hu
Oscillator Flicker Phase Noise: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 538-544 (2021) - [c7]Jianglin Du
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits 2021: 1-2 - 2020
- [c6]Yizhe Hu, Xi Chen
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC 2020: 276-278
2010 – 2019
- 2019
- [j3]Yizhe Hu
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1962-1966 (2019) - [c5]Vivek Govindaraj, Jianglin Du
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS 2019: 81-84 - [c4]Jianglin Du
A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. CICC 2019: 1-4 - [c3]Zhong Gao
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. NEWCAS 2019: 1-4 - 2018
- [j2]Yizhe Hu
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path. IEEE J. Solid State Circuits 53(7): 1977-1987 (2018) - 2017
- [c2]Yizhe Hu
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner. ESSCIRC 2017: 87-90 - 2015
- [c1]Yizhe Hu
A modeling approach for mixed-mode FMCW synthesizer allowing frequency error analysis. ISCAS 2015: 1490-1493 - 2013
- [j1]Xinsheng Wang, Yizhe Hu, Liang Han, Jinghu Li, Chenxu Wang, Mingyan Yu:
A Low Power and variation-Insensitive Current-Mode Signaling Scheme. J. Circuits Syst. Comput. 22(8) (2013)
Coauthor Index
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