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Po-Hsuan Chang
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2020 – today
- 2023
- [c6]Anirban Samanta, Po-Hsuan Chang
, Peng Yan, Mingye Fu, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, Yu Zhang, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, Samuel Palermo, S. J. Ben Yoo:
A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit. OFC 2023: 1-3 - [c5]Po-Hsuan Chang
A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c4]Peng Yan
A 12.5 Gb/s 1.38 mW Inverter-Based Optical Receiver in 28 nm CMOS. MWSCAS 2022: 1-4 - 2020
- [c3]Yuanming Zhu
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS. CICC 2020: 1-4
2010 – 2019
- 2014
- [c2]Po-Hsuan Chang
A 10Gb/s 44.2 dB adaptive equalizer with Duobinary tracking loop in 0.18µm CMOS. ISCAS 2014: 2133-2136 - 2013
- [c1]Sheng-Kai You, Po-Hsuan Chang
A 6Gb/s 40dB burst-mode digitally adaptive equalizer with reference-calibrated overshoot control. SoCC 2013: 79-82
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