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Ningxi Liu
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2020 – today
- 2020
- [c10]Pouyan Bassirian, Divya Duvvuri, Daniel S. Truesdell, Ningxi Liu, Benton H. Calhoun, Steven M. Bowers
:
30.1 A Temperature-Robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X-Band. ISSCC 2020: 460-462
2010 – 2019
- 2019
- [j5]Ningxi Liu
A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time. IEEE J. Solid State Circuits 54(7): 1952-1959 (2019) - [j4]Jesse Moody
Interference Robust Detector-First Near-Zero Power Wake-Up Receiver. IEEE J. Solid State Circuits 54(8): 2149-2162 (2019) - [j3]Christopher J. Lukas
A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications. IEEE Trans. Biomed. Circuits Syst. 13(2): 271-281 (2019) - [j2]Lijun Wang, Dan Zhang, Jinkun Liu, Haifeng Huang, Qiuyue Shi, Ningxi Liu:
Adaptive fault-tolerant control for a joint flexible manipulator based on dynamic surface. Trans. Inst. Meas. Control 41(15): 4240-4253 (2019) - [c9]Angad S. Rekhi
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC 2019: 81 - [c8]Jesse Moody, Anjana Dissanayake
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver. VLSI Circuits 2019: 86- - 2018
- [c7]Ningxi Liu, Rishika Agarwala, Anjana Dissanayake
A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time. ESSCIRC 2018: 150-153 - [c6]Jesse Moody, Pouyan Bassirian
A -76dBm 7.4nW wakeup radio with automatic offset compensation. ISSCC 2018: 452-454 - 2017
- [c5]Arijit Banerjee
A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors. CICC 2017: 1-4 - 2016
- [c4]Harsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton H. Calhoun, Kazuyuki Kumeno, Makoto Yasuda, Akihiko Harada, Taiji Ema:
A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic. ESSCIRC 2016: 45-48 - [c3]Ningxi Liu, Benton H. Calhoun:
Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) Tool. ISVLSI 2016: 535-540 - 2014
- [j1]Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng:
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 423-427 (2014) - 2013
- [c2]Hui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. ASICON 2013: 1-3 - [c1]Ningxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin:
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing. ASICON 2013: 1-4
Coauthor Index
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