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Charles A. Zukowski
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2010 – 2019
- 2010
- [c21]Kagan Irez
, Jiaping Hu, Charles A. Zukowski:
Characteristics of MS-CMOS logic in sub-32nm technologies. ACM Great Lakes Symposium on VLSI 2010: 393-396
2000 – 2009
- 2006
- [c20]Ali Bastani, Charles A. Zukowski:
Monotonic static CMOS tradeoffs in sub-100nm technologies. ACM Great Lakes Symposium on VLSI 2006: 278-283 - [c19]Ali Bastani, Charles A. Zukowski:
A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology. ISQED 2006: 312-317 - 2005
- [j7]Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky:
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. Integr. 38(3): 491-504 (2005) - [c18]Ali Bastani, Charles A. Zukowski:
Characterization of monotonic static CMOS gates in a 65nm technology. ACM Great Lakes Symposium on VLSI 2005: 408-411 - 2004
- [c17]Ali Bastani, Charles A. Zukowski:
Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. ACM Great Lakes Symposium on VLSI 2004: 119-122 - [c16]Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky:
Characterization of logic circuit techniques for high leakage CMOS technologies. ACM Great Lakes Symposium on VLSI 2004: 230-235 - [e1]David Garrett, John C. Lach, Charles A. Zukowski:
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004. ACM 2004, ISBN 1-58113-853-9 [contents] - 2003
- [c15]Ilias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou:
A custom FPGA for the simulation of gene regulatory networks. ACM Great Lakes Symposium on VLSI 2003: 132-135 - 2000
- [j6]Anthony A. Renshaw, Joshua H. Reibel, Charles A. Zukowski, Katie Penn, Robert O. McClintock, Morton B. Friedman:
An assessment of on-line engineering design problem presentation strategies. IEEE Trans. Educ. 43(2): 83-91 (2000) - [c14]Gary L. Dare, Charles A. Zukowski:
Accuracy management for mixed-mode digital VLSI simulation. ACM Great Lakes Symposium on VLSI 2000: 167-170 - [c13]S. Henry Li, Charles A. Zukowski:
Application of dynamic power supply scaling in a low-energy ATM interface. ISCAS 2000: 745-748
1990 – 1999
- 1996
- [c12]Christophe Tretz, Charles A. Zukowski:
CMOS Transistor Sizing for Minimization of Energy-Delay Product. Great Lakes Symposium on VLSI 1996: 168-173 - [c11]Hong Shi, Charles A. Zukowski, Omar Wing:
VLSI Design Optimization of Input/Output-Buffered Broadband ATM Switches. INFOCOM 1996: 810-817 - 1995
- [c10]Hong Shi, Naeem Abbasi, Charles A. Zukowski, Omar Wing:
Buffer size trade-offs in input/output buffered ATM switches under various conditions. ICCCN 1995: 258 - 1994
- [c9]Ying-Wen Bai, Charles A. Zukowski:
Delay-time bounds and waveform bounds for RLCG ladder networks. Annual Simulation Symposium 1994: 23-30 - [c8]Paul Landsberg, Charles A. Zukowski:
Generic Queue Scheduling: Concepts and VLSI. INFOCOM 1994: 1438-1445 - 1993
- [c7]Perng-Shyong Lin, Charles A. Zukowski:
Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. ICCD 1993: 352-356 - [c6]Perng-Shyong Lin, Charles A. Zukowski:
Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies. ISCAS 1993: 2114-2117 - 1992
- [j5]Tong-Bi Pei, Charles A. Zukowski:
Putting routing tables in silicon. IEEE Netw. 6(1): 42-50 (1992) - [j4]Tong-Bi Pei, Charles A. Zukowski:
High-speed parallel CRC circuits in VLSI. IEEE Trans. Commun. 40(4): 653-657 (1992) - [c5]Charles A. Zukowski, Ying-Wen Bai:
Implementing a High-Frequency Pattern Generator Based on Combinational Merging. ICCD 1992: 81-84 - 1991
- [c4]Tong-Bi Pei, Charles A. Zukowski:
VLSI Implementation of Routing Tables: Tries and CAMs. INFOCOM 1991: 515-524 - 1990
- [c3]Charles A. Zukowski, George Gristede, Albert E. Ruehli:
Measuring Error Propagation in Waveform Relaxation Algorithms. ICCAD 1990: 170-173
1980 – 1989
- 1988
- [j3]Lance A. Glasser, Charles A. Zukowski:
Continuous Models for Communication Density Constraints on Multiprocessor Performance. IEEE Trans. Computers 37(6): 652-656 (1988) - [c2]Charles A. Zukowski, De-Ping Chen:
Variable reduction in MOS timing models. ICCD 1988: 124-128 - [c1]Charles A. Zukowski, Kevin Shum:
A matched-delay CMOS TDM multiplexer cell. ICCD 1988: 352-355 - 1986
- [j2]Charles A. Zukowski:
Relaxing Bounds for Linear RC Mesh Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(2): 305-312 (1986) - 1985
- [j1]Jeffrey H. Lang, Charles A. Zukowski, Richard O. LaMaire, Chae H. An:
Integrated-Circuit Logarithmic Arithmetic Units. IEEE Trans. Computers 34(5): 475-483 (1985)
Coauthor Index
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