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Declan Dalton
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2020 – today
- 2022
- [c3]Hyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato:
A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time. ISSCC 2022: 146-148
2010 – 2019
- 2014
- [c2]Jack Kenney, Terry Chen, Larry DeVito, Declan Dalton, Stuart McCracken, Richard Soenneker, Ward S. Titus, Todd S. Weigandt:
A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery. CICC 2014: 1-4
2000 – 2009
- 2006
- [j3]John G. Kenney, Declan Dalton, Eric Evans, Murat Hayri Eskiyerli, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Lawrence DeVito:
A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS. IEEE J. Solid State Circuits 41(12): 2901-2910 (2006) - [c1]Jack Kenney, Declan Dalton, Murat Hayri Eskiyerli, Eric Evans, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Larry DeVito:
A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS. ISSCC 2006: 864-873 - 2005
- [j2]Declan Dalton, Kwet Chai, Eric Evans, Mark A. Ferriss, Dave Hitchcox, Paul Murray, Sivanendra Selvanayagam, Paul Shepherd, Lawrence DeVito:
A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback. IEEE J. Solid State Circuits 40(12): 2713-2725 (2005)
1990 – 1999
- 1999
- [j1]Iuri Mehr, Declan Dalton:
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications. IEEE J. Solid State Circuits 34(7): 912-920 (1999)
Coauthor Index
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