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Sanjeev Mehta
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2010 – 2019
- 2019
- [c6]Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya:
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. VLSID 2019: 305-310 - [c5]Hari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini
, Arup Roy Chowdhury, A. S. Kiran Kumar, Dinesh Kumar Sharma:
Large Dynamic Range Readout Integrated Circuit for Infrared Detectors. VLSID 2019: 311-316 - 2015
- [c4]Hari Shanker Gupta, Shweta Kirkire, Sunil Bhati, Ravi Shankar Chaurasia, Sanjeev Mehta, Arup Roy Choudhary, Dipen Patel, Jaymin Vaghela:
Bipolar voltage level shifter. VDAT 2015: 1-5 - [c3]Mohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury:
An all digital delay lock loop architecture for high precision timing generator. VDAT 2015: 1-6 - 2014
- [c2]Parth Shah, Bhavesh Soni
Generic and programmable Timing Generator for CCD detectors. ICACCI 2014: 1845-1851 - [c1]Hari Shanker Gupta, Subhananda Chakrabarti
Implementation of high performance Readout Integrated Circuit. MWSCAS 2014: 402-405
Coauthor Index
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last updated on 2024-04-25 05:58 CEST by the dblp team
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