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Abinash Mohanty
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2020 – today
- 2024
- [j4]Anupreetham Anupreetham
, Mohamed Ibrahim
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. 17(1): 1:1-1:20 (2024) - 2021
- [c10]Anupreetham Anupreetham
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL 2021: 76-82
2010 – 2019
- 2019
- [j3]Minkyu Kim
A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3843-3853 (2019) - [i1]Xiaocong Du, Gokul Krishnan, Abinash Mohanty, Zheng Li, Gouranga Charan, Yu Cao:
Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches. CoRR abs/1906.08866 (2019) - 2018
- [b1]Abinash Mohanty:
Algorithm and Hardware Design for Efficient Deep Learning Inference. Arizona State University, Tempe, USA, 2018 - [c9]Prad Kadambi, Abinash Mohanty
Towards a Wearable Cough Detector Based on Neural Networks. ICASSP 2018: 2161-2165 - 2017
- [j2]Abinash Mohanty
RTN in Scaled Transistors for On-Chip Random Seed Generation. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2248-2257 (2017) - [c8]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC 2017: 21-22 - [c7]Minkyu Kim, Abinash Mohanty
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS 2017: 1-4 - 2016
- [c6]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c5]Abinash Mohanty
High-performance face detection with CPU-FPGA acceleration. ISCAS 2016: 117-120 - 2015
- [j1]Deepak Kadetotad, Zihan Xu, Abinash Mohanty
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 194-204 (2015) - [c4]Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE 2015: 854-859 - [c3]Ketul B. Sutaria, Pengpeng Ren, Abinash Mohanty
Duty cycle shift under static/dynamic aging in 28nm HK-MG technology. IRPS 2015: 7 - 2014
- [c2]Zihan Xu, Abinash Mohanty
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA 2014: 126-133 - [c1]Deepak Kadetotad
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS 2014: 536-539
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