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Nilanjan Mukherjee

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This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.

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2020 – today

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2023
[c5]
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  - conf/iecon/MukherjeeS23
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Nilanjan Mukherjee, Sudeshna Sarkar:
An Approach to Battery Pack Balancing Control Optimizing the Usable Capacity of the Battery Pack. IECON 2023: 1-6
[c4]
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Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee:
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. ITC 2023: 1-10
2022
[c3]
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Minqiang Peng, Youfa Wu, Jialiang Li, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutyunyan, Yervant Zorian, Nilanjan Mukherjee:
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety. VTS 2022: 1

1990 – 1999

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1998
[j2]
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Nilanjan Mukherjee, Ramesh Karri:
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures. J. Electron. Test. 13(2): 189-200 (1998)
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Ramesh Karri, Nilanjan Mukherjee:
Versatile BIST: an integrated approach to on-line/off-line BIST. ITC 1998: 910-917
1995
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Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An ILP Solution for Optimum Scheduling, Module and Register Allocation, and Operation Binding in Datapath Synthesis. VLSI Design 3(1): 21-36 (1995)
1993
[c1]
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Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji:
An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. VLSI Design 1993: 192-197

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