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Zhengya Zhang
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2020 – today
- 2024
- [j38]Wei Tang
, Sung-Gun Cho
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59(4): 1235-1245 (2024) - [j37]Jie-Fang Zhang
TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing. IEEE Trans. Computers 73(5): 1219-1232 (2024) - [j36]Fan-Hsuan Meng, Yuting Wu
TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1172-1183 (2024) - [c69]Vikram Jain
Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED 2024: 1-6 - [c68]Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee:
2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. ISSCC 2024: 50-52 - [c67]Cheng-Hsun Lu, Wei Tang, Jiyoon Han, Zhengya Zhang:
An 11.4mm2 40.2Gbps 17.4pJ/b/Iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communications. VLSI Technology and Circuits 2024: 1-2 - [c66]Jiyoon Han, Canan Cebeci, Wei Tang, Zhengya Zhang, Upamanyu Madhow:
Tiled Beamspace Processing for Scaling mmWave Massive MU-MIMO. VTC Fall 2024: 1-6 - 2023
- [j35]Reid Pinkham
ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1256-1269 (2023) - [c65]Junkang Zhu
eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs. HPCA 2023: 802-813 - [c64]Teyuh Chou, Fernando García-Redondo
AR-PIM: An Adaptive-Range Processing-in-Memory Architecture. ISLPED 2023: 1-6 - [c63]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j34]Junkang Zhu
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. IEEE J. Solid State Circuits 57(11): 3490-3502 (2022) - [j33]Xinxin Wang
TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 559-563 (2022) - [c62]Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang:
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. VLSI Technology and Circuits 2022: 208-209 - [c61]Justin M. Correll
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits 2022: 264-265 - [i6]Yaoyu Tao, Zhengya Zhang:
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. CoRR abs/2202.07275 (2022) - [i5]Yaoyu Tao, Shuanghong Sun, Zhengya Zhang:
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. CoRR abs/2202.07284 (2022) - 2021
- [j32]Reid Pinkham
Near-Sensor Distributed DNN Processing for Augmented and Virtual Reality. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 663-676 (2021) - [j31]Yaoyu Tao
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. IEEE J. Solid State Circuits 56(2): 612-623 (2021) - [j30]Jie-Fang Zhang
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. IEEE J. Solid State Circuits 56(2): 636-647 (2021) - [j29]Wei Tang
A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. IEEE J. Solid State Circuits 56(6): 1722-1731 (2021) - [c60]Chester Liu, Jacob Botimer, Zhengya Zhang
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. CICC 2021: 1-2 - [c59]Yaoyu Tao, Zhengya Zhang
DNC-Aided SCL-Flip Decoding of Polar Codes. GLOBECOM 2021: 1-6 - [c58]Yaoyu Tao, Zhengya Zhang
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. MICRO 2021: 845-856 - [c57]Jie-Fang Zhang
Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning. MICRO 2021: 1078-1090 - [c56]Jie-Fang Zhang
Exploration of Energy-Efficient Architecture for Graph-Based Point-Cloud Deep Learning. SiPS 2021: 260-264 - [c55]Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits 2021: 1-2 - [c54]Junkang Zhu
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. VLSI Circuits 2021: 1-2 - [i4]Yaoyu Tao, Zhengya Zhang:
DNC-Aided SCL-Flip Decoding of Polar Codes. CoRR abs/2101.10498 (2021) - 2020
- [j28]Thomas Chen
A 1.87-mm2 56.9-GOPS Accelerator for Solving Partial Differential Equations. IEEE J. Solid State Circuits 55(6): 1709-1718 (2020) - [c53]Reid Pinkham, Shuqing Zeng, Zhengya Zhang
QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. HPCA 2020: 180-192 - [c52]Zhengya Zhang, Anke Klingner, Sarthak Misra, Islam S. M. Khalil
Control of Magnetically-Driven Screws in a Viscoelastic Medium. IROS 2020: 2840-2846
2010 – 2019
- 2019
- [j27]Wei Tang
A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS. IEEE J. Solid State Circuits 54(7): 2070-2080 (2019) - [j26]Thomas Chen
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification. IEEE J. Solid State Circuits 54(7): 2081-2090 (2019) - [j25]Yaoyu Tao
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 4032-4043 (2019) - [j24]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c51]Thomas Chen, Jacob Botimer, Teyuh Chou, Zhengya Zhang
An Sram-Based Accelerator for Solving Partial Differential Equations. CICC 2019: 1-4 - [c50]Sung-Gun Cho, Edith Beigné, Zhengya Zhang
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC 2019: 1-4 - [c49]Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. MICRO 2019: 114-125 - [c48]Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. VLSI Circuits 2019: 240- - [c47]Jie-Fang Zhang
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. VLSI Circuits 2019: 306- - 2018
- [j23]Ziyun Li
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. IEEE J. Solid State Circuits 53(1): 76-90 (2018) - [j22]Chester Liu
A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. IEEE J. Solid State Circuits 53(10): 2818-2827 (2018) - [j21]Shiming Song
A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2269-2278 (2018) - [j20]Mohammed Affan Zidan
Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. IEEE Trans. Multi Scale Comput. Syst. 4(4): 698-710 (2018) - [c46]Chester Liu, Zhengya Zhang
Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm. BioCAS 2018: 1-4 - [c45]Shiming Song, Wei Tang, Thomas Chen, Zhengya Zhang
LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS. CICC 2018: 1-4 - [c44]Hsi-Shou Wu, Zhengya Zhang
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. ESSCIRC 2018: 162-165 - [c43]Wei Tang, Hemanth Prabhu, Liang Liu
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. ISSCC 2018: 224-226 - [c42]Zhengya Zhang, Matilde Santos
Optimizing a Fuzzy Equivalent Sliding Mode Control Applied to Servo Drive Systems. SOCO-CISIS-ICEUTE 2018: 303-312 - 2017
- [j19]Shuanghong Sun
Designing Practical Polar Codes Using Simulation-Based Bit Selection. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 594-603 (2017) - [j18]John Bell
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. IEEE J. Solid State Circuits 52(5): 1450-1457 (2017) - [j17]Krishnendu Chakrabarty
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c41]Shengshuo Lu, Zhengya Zhang
A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices. A-SSCC 2017: 65-68 - [c40]Chester Liu, Sung-Gun Cho, Zhengya Zhang
A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. A-SSCC 2017: 233-236 - [c39]Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang
Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes. GLOBECOM 2017: 1-6 - [c38]Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. ISSCC 2017: 62-63 - [c37]Hsi-Shou Wu, Zhengya Zhang
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. ISSCC 2017: 348-349 - 2016
- [j16]Haichang Gao, Xuqin Wang, Fang Cao, Zhengya Zhang, Lei Lei, Jiao Qi, Xiyang Liu:
Robustness of text-based completely automated public turing test to tell computers and humans apart. IET Inf. Secur. 10(1): 45-52 (2016) - [j15]Farhana Sheikh
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. J. Signal Process. Syst. 84(3): 295-307 (2016) - [c36]Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang
Error patterns in belief propagation decoding of polar codes and their mitigation methods. ACSSC 2016: 1199-1203 - [c35]Shengshuo Lu, Zhengya Zhang
A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh. A-SSCC 2016: 133-136 - [c34]Todd Gaier, Pekka Kangaslahti, Bjorn Lambrigtsen, Isaac Ramos-Pérez, Alan B. Tanner, Darren McKague
A 180 GHz prototype for a geostationary microwave imager/sounder-GeoSTAR-III. IGARSS 2016: 2021-2023 - [c33]Shuanghong Sun, Zhengya Zhang
Architecture and optimization of high-throughput belief propagation decoding of polar codes. ISCAS 2016: 165-168 - [c32]Haichang Gao, Jeff Yan, Fang Cao, Zhengya Zhang, Lei Lei, Mengyun Tang, Ping Zhang, Xin Zhou, Xuqin Wang, Jiawei Li:
A Simple Generic Attack on Text Captchas. NDSS 2016 - [c31]Phil Knag, Chester Liu, Zhengya Zhang
A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. VLSI Circuits 2016: 1-2 - [c30]Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. VLSI Circuits 2016: 1-2 - [i3]Mohammed Affan Zidan, YeonJoo Jeong, Jong Hoon Shin, Chao Du, Zhengya Zhang, Wei D. Lu:
Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. CoRR abs/1612.02913 (2016) - 2015
- [j14]Yen-Po Chen, Dongsuk Jeon, Yoonmyung Lee
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. IEEE J. Solid State Circuits 50(1): 375-390 (2015) - [j13]Youn Sung Park, Yaoyu Tao, Zhengya Zhang
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. IEEE J. Solid State Circuits 50(2): 464-475 (2015) - [j12]Phil Knag, Jung Kuk Kim, Thomas Chen, Zhengya Zhang
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding. IEEE J. Solid State Circuits 50(4): 1070-1079 (2015) - [j11]Chia-Hsiang Chen, Shiming Song, Zhengya Zhang
An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 471-475 (2015) - [c29]Tai-Chuan Ou, Zhengya Zhang
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. A-SSCC 2015: 1-4 - [c28]Chia-Hsiang Chen, Wei Tang, Zhengya Zhang
18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. ISSCC 2015: 1-3 - [c27]Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning. VLSIC 2015: 50- - [c26]Shengshuo Lu, Zhengya Zhang
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. VLSIC 2015: 246- - 2014
- [j10]Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. IEEE J. Solid State Circuits 49(3): 783-794 (2014) - [j9]Dongsuk Jeon, Michael B. Henry, Yejoong Kim
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. IEEE J. Solid State Circuits 49(5): 1271-1284 (2014) - [j8]Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
Efficient Hardware Architecture for Sparse Coding. IEEE Trans. Signal Process. 62(16): 4173-4186 (2014) - [j7]Chia-Hsiang Chen, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
Design and Evaluation of Confidence-Driven Error-Resilient Systems. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1727-1737 (2014) - [c25]Siddharth Gaba, Phil Knag, Zhengya Zhang
Memristive devices for stochastic computing. ISCAS 2014: 2592-2595 - [c24]Dongsuk Jeon, Yen-Po Chen, Yoonmyung Lee
24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. ISSCC 2014: 416-417 - [c23]Tai-Chuan Ou, Zhengya Zhang
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. ISSCC 2014: 462-463 - [c22]Farhana Sheikh
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. SiPS 2014: 192-197 - [c21]Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
A 6.67mW sparse coding ASIC enabling on-chip learning and inference. VLSIC 2014: 1-2 - [c20]Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. VLSIC 2014: 1-2 - 2013
- [c19]Chia-Hsiang Chen, Shiming Song, Zhengya Zhang:
An FPGA-based transient error simulator for evaluating resilient system designs (abstract only). FPGA 2013: 271 - [c18]Dongsuk Jeon, Yejoong Kim
A low-power VGA full-frame feature extraction processor. ICASSP 2013: 2726-2730 - [c17]Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang
Efficient in situ error detection enabling diverse path coverage. ISCAS 2013: 773-776 - [c16]Chia-Hsiang Chen, Keith A. Bowman
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED 2013: 181-186 - [c15]Dongsuk Jeon, Yejoong Kim
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. ISSCC 2013: 166-167 - [c14]Youn Sung Park, Yaoyu Tao, Zhengya Zhang
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. ISSCC 2013: 422-423 - 2012
- [j6]Dongsuk Jeon, Mingoo Seok, Zhengya Zhang
Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 952-956 (2012) - [j5]Jung Kuk Kim, Jeffrey A. Fessler, Zhengya Zhang
Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-Ray CT. IEEE Trans. Signal Process. 60(10): 5508-5518 (2012) - [c13]Haoran Li, Youn Sung Park, Zhengya Zhang
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. FPGA 2012: 167-170 - [c12]Yaoyu Tao, Youn Sung Park, Zhengya Zhang
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. ISCAS 2012: 2625-2628 - [c11]Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. VLSIC 2012: 114-115 - [i2]Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel:
The Cycle Consistency Matrix Approach to LDPC Absorbing Sets in Separable Circulant-Based Codes. CoRR abs/1208.6094 (2012) - 2011
- [c10]Chia-Hsiang Chen, Yejoong Kim
A confidence-driven model for error-resilient computing. DATE 2011: 1608-1613 - [c9]Jung Kuk Kim, Zhengya Zhang
Hardware acceleration of iterative image reconstruction for X-ray computed tomography. ICASSP 2011: 1697-1700 - [c8]Matthew Weiner, Borivoje Nikolic
LDPC decoder architecture for high-data rate personal-area networks. ISCAS 2011: 1784-1787 - [c7]Jiadong Wang, Lara Dolecek, Zhengya Zhang
Absorbing set spectrum approach for practical code design. ISIT 2011: 2726-2730 - [i1]Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel:
Absorbing Set Spectrum Approach for Practical Code Design. CoRR abs/1106.0057 (2011) - 2010
- [j4]Zhengya Zhang
An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors. IEEE J. Solid State Circuits 45(4): 843-855 (2010) - [j3]Lara Dolecek, Zhengya Zhang
Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes. IEEE Trans. Inf. Theory 56(1): 181-201 (2010)
2000 – 2009
- 2009
- [j2]Lara Dolecek, Pamela Lee, Zhengya Zhang
Predicting error floors of structured LDPC codes: deterministic bounds and estimates. IEEE J. Sel. Areas Commun. 27(6): 908-917 (2009) - [j1]Zhengya Zhang
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices. IEEE Trans. Commun. 57(11): 3258-3268 (2009) - 2008
- [c6]Zhengya Zhang
Lowering LDPC Error Floors by Postprocessing. GLOBECOM 2008: 3074-3079 - [c5]Pamela Lee, Lara Dolecek, Zhengya Zhang
Error floors in LDPC codes: Fast simulation, bounds and hardware emulation. ISIT 2008: 444-448 - 2007
- [c4]Zhengya Zhang
Quantization Effects in Low-Density Parity-Check Decoders. ICC 2007: 6231-6237 - [c3]Lara Dolecek, Zhengya Zhang
Analysis of Absorbing Sets for Array-Based LDPC Codes. ICC 2007: 6261-6268 - [c2]Zhengya Zhang
Peak-to-Average Power Ratio Reduction in an FDM Broadcast System. SiPS 2007: 25-30 - 2006
- [c1]Zhengya Zhang
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation. GLOBECOM 2006
Coauthor Index
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