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Pei-Yuan Chou
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2020 – today
- 2024
- [j3]Jinn-Shyan Wang
, Pei-Yuan Chou
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3157-3164 (2024)
2010 – 2019
- 2019
- [j2]Pei-Yuan Chou
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2508-2518 (2019) - 2018
- [c5]Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang:
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC 2018: 250-253 - 2017
- [c4]Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON 2017: 68-71 - 2016
- [c3]Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang:
Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. ASP-DAC 2016: 262-267 - 2015
- [j1]Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang:
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. IEEE J. Solid State Circuits 50(11): 2635-2644 (2015) - [c2]Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON 2015: 1-4 - 2014
- [c1]Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang:
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. A-SSCC 2014: 361-364
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