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S. Sioncke
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2010 – 2019
- 2018
- [c3]Vamsi Putcha, Jacopo Franco, Abhitosh Vais
, Ben Kaczer, S. Sioncke, Dimitri Linten, Guido Groeseneken
Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps. IRPS 2018: 5 - 2016
- [c2]Nadine Collaert
Beyond-Si materials and devices for more Moore and more than Moore applications. ICICDT 2016: 1-5 - 2015
- [c1]Abhitosh Vais
The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices. IRPS 2015: 5
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last updated on 2024-10-07 21:23 CEST by the dblp team
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