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G. S. Visweswaran
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2010 – 2019
- 2019
- [c22]Ashish Kumar, Mohammad Aftab Alam, Gangaikondan S. Visweswaran:
A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression Scheme. VLSID 2019: 547-548 - 2018
- [c21]Ashish Kumar, G. S. Visweswaran:
A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias. VLSID 2018: 261-265 - 2017
- [j5]Anuj Grover
, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2438-2447 (2017) - [j4]Roohie Kaushik, Shouri Chatterjee
Charge-Controlled Oscillators and Their Application in Frequency Synthesis. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1127-1131 (2017) - 2016
- [j3]Paramjeet Singh Sahni, Suresh Chandra Joshi, Nitin Gupta, Gangaikondan Subramani Visweswaran:
An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2803-2807 (2016) - [c20]Nidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad S. Hashmi
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation. SoCC 2016: 47-51 - [c19]Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. SoCC 2016: 290-295 - [c18]Nidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. VDAT 2016: 1-6 - [c17]Ashish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha:
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. VLSID 2016: 191-195 - [c16]Surya Piplani, G. S. Visweswaran, Anshul Kumar:
Impact of crosstalk and process variation on capture power reduction for at-speed test. VTS 2016: 1-6 - 2015
- [c15]Ashish Kumar, G. S. Visweswaran, Kaushik Saha:
Low voltage error resilient SRAM using run-time error detection and correction. ESSCIRC 2015: 335-338 - [c14]Anuj Grover
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. ICICDT 2015: 1-4 - [c13]Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha:
A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation. ICICDT 2015: 1-4 - 2011
- [j2]Maneesha Gupta
Digital fractional-order differentiator and integrator models based on first-order and higher order operators. Int. J. Circuit Theory Appl. 39(5): 461-474 (2011) - [j1]G. S. Visweswaran, Pragya Varshney, Maneesha Gupta
New Approach to Realize Fractional Power in z-Domain at Low Frequency. IEEE Trans. Circuits Syst. II Express Briefs 58-II(3): 179-183 (2011) - 2010
- [c12]Lalit K. Jiwani, Shiv Dutt Joshi, G. S. Visweswaran:
FFT based sign modulated DWT filter bank. EUSIPCO 2010: 1489-1893
2000 – 2009
- 2008
- [c11]B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran:
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ICCAD 2008: 559-564 - [c10]Maneesha Gupta, Pragya Varshney, G. S. Visweswaran, B. Kumar:
Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models. SIGMAP 2008: 47-54 - 2006
- [c9]Venkat Rao, Nicolas Navet, Gaurav Singhal, Anshul Kumar, G. S. Visweswaran:
Battery aware dynamic scheduling for periodic task graphs. IPDPS 2006 - 2005
- [c8]Mukul Milind Ojha, Arun Kumar Anand, G. S. Visweswaran, D. Nagchoudhuri:
A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip. VLSI Design 2005: 828-831 - 2004
- [c7]Tushar S. Shelar, G. S. Visweswaran:
Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. VLSI Design 2004: 821-826 - 2000
- [c6]Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran:
Jitter Estimation Methodology for Clock Chips. VLSI Design 2000: 480-482 - [c5]Sanjeev Kumar Maheshwari, G. S. Visweswaran:
A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer. VLSI Design 2000: 484-487
1990 – 1999
- 1999
- [c4]Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi:
A Low Power 256 KB SRAM Design. VLSI Design 1999: 67-71 - [c3]Basabi Bhaumik, G. S. Visweswaran, R. Lakshminarasimhan:
A New Test Compression Scheme. VLSI Design 1999: 95-99 - 1998
- [c2]Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri:
Current Mode Ternary D/A Converter. VLSI Design 1998: 244-248 - 1997
- [c1]Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri:
Micropipeline Architecture for Multiplier-less FIR Filters. VLSI Design 1997: 451-456
Coauthor Index
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