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Haechang Lee
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Haechang Lee 0001 — Seoul National University, Korea (and 1 more)
- Haechang Lee 0002 — Samsung Electronics, Korea
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2020 – today
- 2023
- [j6]Dongsuk Yoo
, Youngtae Jang, Youngchan Kim
Automotive 2.1 μm Full-Depth Deep Trench Isolation CMOS Image Sensor with a 120 dB Single-Exposure Dynamic Range. Sensors 23(22): 9150 (2023)
2010 – 2019
- 2017
- [j5]Yousr Ismail
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology. IEEE J. Solid State Circuits 52(3): 781-798 (2017) - 2015
- [j4]Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. IEEE J. Solid State Circuits 50(1): 291-302 (2015) - [c9]Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang:
Arria™ 10 device architecture. CICC 2015: 1-8 - 2014
- [c8]Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti
12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator. ISSCC 2014: 226-227 - [c7]Yousr Ismail, Haechang Lee, Sudhakar Pamarti
23.8 A 34V charge pump in 65nm bulk CMOS technology. ISSCC 2014: 408-409 - 2013
- [j3]Michael H. Perrott, James C. Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter. IEEE J. Solid State Circuits 48(1): 276-291 (2013) - 2012
- [c6]Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti
A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability. ISSCC 2012: 206-208 - 2011
- [c5]Andrew K. Joy, Hugh Mair, Hae-Chang Lee, Arnold Feldman, Clemenz L. Portmann, Neil Bulman, Eugenia Cordero Crespo, Peter Hearne, Patty Huang, Ben Kerr, Pulkit Khandelwal, Franz Kuhlmann, Shaun Lytollis, Joaquim Machado, Casey Morrison, Scott Morrison, Shahriar Rabii, Dushmantha Rajapaksha, Vishnu Ravinuthula, Giuseppe Surace:
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver. ISSCC 2011: 350-351 - 2010
- [c4]Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner
Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC 2010: 176-177
2000 – 2009
- 2009
- [j2]Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi:
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44(4): 1235-1247 (2009) - 2008
- [j1]E-Hung Chen, Jihong Ren, Brian S. Leibowitz, Hae-Chang Lee, Qi Lin, Kyung Suk Oh, Frank Lambrecht, Vladimir Stojanovic
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric. IEEE J. Solid State Circuits 43(9): 2144-2156 (2008) - [c3]Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang:
Clocking circuits for a 16Gb/s memory interface. CICC 2008: 435-438 - 2007
- [c2]Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. ISSCC 2007: 228-599 - 2006
- [c1]Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz:
Improving CDR Performance via Estimation. ISSCC 2006: 1296-1303
Coauthor Index
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