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Andre Szczepanek
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2010 – 2019
- 2012
- [c2]Mike Harwood, Steffen Nielsen, Andre Szczepanek, Richard Allred, Sean Batty, Mike Case, Simon Forey, Karthik Gopalakrishnan, Larry Kan, Bob Killips, Parmanand Mishra, Rohit Pande, Hamid Rategh, Alan Ren, Jeff Sanders, Albrecht Schoy, Richard Ward, Martin Wetterhorn, Norman Yeung:
A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications. ISSCC 2012: 326-327
2000 – 2009
- 2007
- [c1]Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth:
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery. ISSCC 2007: 436-591
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last updated on 2024-04-25 05:55 CEST by the dblp team
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