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Javier E. Soto
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2020 – today
- 2024
- [c6]Carolina Gallardo-Pavesi, Yaime Fernández, Javier E. Soto, Cecilia Hernández, Miguel E. Figueroa:
A Hardware Accelerator for Quantile Estimation of Network Packet Attributes. DSD 2024: 114-121 - 2023
- [j5]Yaime Fernández
, Javier E. Soto
A streaming algorithm and hardware accelerator to estimate the empirical entropy of network flows. Comput. Networks 237: 110035 (2023) - [j4]Javier E. Soto, Cecilia Hernández
JACC-FPGA: A hardware accelerator for Jaccard similarity estimation using FPGAs in the cloud. Future Gener. Comput. Syst. 138: 26-42 (2023) - [c5]Javier E. Soto, Sofía Vera, Yaime Fernández, Daniel Yunge, Cecilia Hernández, Miguel E. Figueroa:
A Sketch-Based Algorithm for Network-Flow Entropy Estimation on Programmable Switches Using P4. DSD 2023: 79-86 - 2021
- [j3]Javier E. Soto
A High-Throughput Hardware Accelerator for Network Entropy Estimation Using Sketches. IEEE Access 9: 85823-85838 (2021) - [j2]Wladimir E. Valenzuela
Face Recognition on a Smart Image Sensor Using Local Gradients. Sensors 21(9): 2901 (2021) - 2020
- [j1]Javier Cardenas, Javier E. Soto, Miguel E. Figueroa:
Multimodal registration of visible, SWIR and LWIR images in a distributed smart camera system. Microprocess. Microsystems 73: 102987 (2020) - [c4]Javier E. Soto, Paulo Ubisse, Cecilia Hernández
A hardware accelerator for entropy estimation using the top-k most frequent elements. DSD 2020: 141-148
2010 – 2019
- 2019
- [c3]Javier E. Soto, Thomas Krohmer, Cecilia Hernández
Hardware Acceleration of k-Mer Clustering using Locality-Sensitive Hashing. DSD 2019: 659-662 - 2017
- [c2]Silvana Diaz, Javier E. Soto, Fabian Inostroza, Sebastián E. Godoy
An embedded system for image segmentation and multimodal registration in noninvasive skin cancer screening. EMBC 2017: 636-639 - [c1]Javier E. Soto, Wladimir E. Valenzuela
An intelligent readout integrated circuit (iROIC) with on-chip local gradient operations. ICECS 2017: 360-362 - 2014
- [b1]Javier E. Soto:
Proposal and development of a highly modular and scalable self-adaptive hardware architecture with parallel processing capability. Polytechnic University of Catalonia, Spain, 2014
Coauthor Index
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last updated on 2024-11-20 20:52 CET by the dblp team
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