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Huong Ho
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2020 – today
- 2021
- [c2]Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto:
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. ISSCC 2021: 132-134
2010 – 2019
- 2019
- [c1]Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho, Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto:
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss. ISSCC 2019: 114-116 - 2014
- [j4]Huong Ho:
Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m). J. Signal Process. Syst. 75(3): 203-208 (2014) - 2011
- [j3]Huong Ho, Robert Klepko, Nam Ninh, Demin Wang:
A high performance hardware architecture for multi-frame hierarchical motion estimation. IEEE Trans. Consumer Electron. 57(2): 794-801 (2011) - 2010
- [j2]Huong Ho, Valek Szwarc, Tad A. Kwasniewski:
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. J. Signal Process. Syst. 61(3): 353-365 (2010)
2000 – 2009
- 2009
- [j1]Huong Ho, Valek Szwarc, Tad A. Kwasniewski:
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. Int. J. Reconfigurable Comput. 2009: 529512:1-529512:14 (2009)
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