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Ye-Dam Kim
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- affiliation: KAIST, Yuseong-gu, Daejeon, South Korea
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2020 – today
- 2024
- [j7]Jae-Hyun Chung
, Ye-Dam Kim
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. IEEE J. Solid State Circuits 59(8): 2481-2491 (2024) - [j6]Dong-Hun Lee
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. IEEE J. Solid State Circuits 59(10): 3232-3241 (2024) - [c9]Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Chang-Un Park, Kun-Woo Park, Kwan-Hoon Song, Young-Hun Moon, Min-Jae Seo, Seung-Tak Ryu:
A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. VLSI Technology and Circuits 2024: 1-2 - [c8]Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c7]Kent Edrian Lozada
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. A-SSCC 2023: 1-3 - [c6]Jae-Hyun Chung, Ye-Dam Kim
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. CICC 2023: 1-2 - 2022
- [j5]Kent Edrian Lozada
A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3635-3639 (2022) - 2021
- [j4]Dong-Ryeol Oh
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. IEEE J. Solid State Circuits 56(4): 1216-1226 (2021) - [c5]Ye-Dam Kim
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. A-SSCC 2021: 1-3 - 2020
- [j3]Min-Jae Seo
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. IEEE J. Solid State Circuits 55(10): 2660-2669 (2020) - [c4]Dong-Ryeol Oh
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c3]Min-Jae Seo
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC 2019: 189-192 - [c2]Min-Jae Seo
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. VLSI Circuits 2019: 72- - [c1]Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. VLSI Circuits 2019: 138- - 2018
- [j2]Min-Jae Seo
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3617-3627 (2018) - [j1]Min-Jae Seo
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1904-1908 (2018)
Coauthor Index
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