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Rajesh Pamula 0001
Person information
- affiliation: University of Washington, Department of Electrical and Computer Engineering, Seattle, WA, USA
Other persons with the same name
- Pamula Venkata Rajesh 0002 (aka: Venkata Rajesh Pamula 0002, V. Rajesh Pamula 0002) — IMEC, Belgium (and 1 more)
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2020 – today
- 2022
- [j7]Chi-Hsiang Huang
, Yidong Chen, Xun Sun
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57(1): 90-102 (2022) - 2021
- [c10]Arindam Mandal, Diego Peña, Rajesh Pamula, Karam Khateeb, Logan Murphy, Azadeh Yazdan-Shahmorad, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe:
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation. CICC 2021: 1-2 - [c9]Chi-Hsiang Huang
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. ISSCC 2021: 416-418 - 2020
- [j6]Fahim ur Rahman
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. IEEE J. Solid State Circuits 55(2): 494-504 (2020) - [j5]John P. Uehlin
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS. IEEE J. Solid State Circuits 55(7): 1749-1761 (2020) - [j4]John P. Uehlin
A 0.0023 mm2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression. IEEE Trans. Biomed. Circuits Syst. 14(2): 319-331 (2020) - [c8]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits 2020: 1-2 - [c7]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j3]Fahim ur Rahman
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54(4): 1173-1184 (2019) - [j2]Xun Sun
An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54(11): 3215-3225 (2019) - [c6]John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell:
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS. ESSCIRC 2019: 77-80 - [c5]Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe:
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. ISSCC 2019: 230-232 - [c4]Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe:
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. ISSCC 2019: 312-314 - 2018
- [j1]Vincent T. Lee
Architecture Considerations for Stochastic Computing Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2277-2289 (2018) - [c3]Xun Sun, Sung Kim
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC 2018: 302-304 - [c2]Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe:
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits 2018: 1-2 - [c1]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits 2018: 65-66
Coauthor Index
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