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Jan Lappas
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2020 – today
- 2024
- [c7]Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif:
Timing Analysis beyond Complementary CMOS Logic Styles. ASPDAC 2024: 189-194 - [c6]Mohammadreza Esmaeilpour, Jan Lappas, Hussien Abdo, Christian Weis, Norbert Wehn:
A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces. NewCAS 2024: 55-59 - 2022
- [j4]Chirag Sudarshan
, Taha Soliman, Jan Lappas, Christian Weis
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 367-380 (2022) - [c5]Jan Lappas, André Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni
Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node. DATE 2022: 1083-1084 - [c4]Zhe Zhang, Jan Lappas, André Lucas Chinazzo, Christian Weis, Zhihang Wu, Leibin Ni
Machine learning based soft error rate estimation of pass transistor logic in high-speed communication. ETS 2022: 1-4 - [c3]André Lucas Chinazzo, Jan Lappas, Christian Weis, Qinhui Huang, Zhihang Wu, Leibin Ni
Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology. ICECS 2022 2022: 1-4 - 2021
- [j3]Chirag Sudarshan
A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1615-1619 (2021) - [j2]Vladimir Rybalkin
Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 93(12): 1467 (2021) - 2020
- [j1]Vladimir Rybalkin
Efficient Hardware Architectures for 1D- and MD-LSTM Networks. J. Signal Process. Syst. 92(11): 1219-1245 (2020)
2010 – 2019
- 2019
- [c2]Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn
An In-DRAM Neural Network Processing Engine. ISCAS 2019: 1-5 - [c1]Chirag Sudarshan, Jan Lappas, Christian Weis, Deepak M. Mathew, Matthias Jung, Norbert Wehn
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. SAMOS 2019: 429-441
Coauthor Index
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