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Byeonghun Yun
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2020 – today
- 2024
- [j8]Abdul Qahir
, Dzuhri Radityo Utomo
High-Power 150/245-GHz Fundamental Oscillators With 12.1/-2.54-dBm Peak Output Power for Phased Array Transceivers. IEEE J. Solid State Circuits 59(11): 3683-3693 (2024) - 2023
- [j7]Byeong-Taek Moon
Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques. IEEE Access 11: 34942-34951 (2023) - [j6]Keun-Mok Kim
A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency. IEEE J. Solid State Circuits 58(6): 1667-1680 (2023) - [j5]Byeonghun Yun
H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized Gmax-Core and Transmission Line-Based Zero-Degree Power Combining Networks. IEEE J. Solid State Circuits 58(11): 3089-3102 (2023) - [j4]Hyo-Ryeong Jeon
A 250-GHz Wideband Direct-Conversion CMOS Receiver Adopting Baseband Equalized Low-Loss Resistive Passive Mixer. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3852-3856 (2023) - 2022
- [c5]Keun-Mok Kim, Kyung-Sik Choi, Hyunki Jung, Byeonghun Yun, Subin Kim, Wonkab Oh, Eui-Soo Lee, Sujin Park, Eui-Rim Jeong, Jinho Ko, Sang-Gug Lee:
An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver. ISSCC 2022: 404-406 - 2021
- [j3]Dae-Woong Park
A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core. IEEE Access 9: 99039-99049 (2021) - [j2]Keun-Mok Kim
A -123-dBm Sensitivity Split-Channel BFSK Reconfigurable Data/Wake-Up Receiver for Low-Power Wide-Area Networks. IEEE J. Solid State Circuits 56(9): 2656-2667 (2021) - [j1]Dae-Woong Park
Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-Gmax Gain Boosting Technique. IEEE J. Solid State Circuits 56(11): 3388-3398 (2021) - [c4]Byeonghun Yun, Dae-Woong Park, Kyung-Sik Choi, Ho-Jin Song, Sang-Gug Lee:
245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power Combining. A-SSCC 2021: 1-3 - 2020
- [c3]Kyung-Sik Choi, Dzuhri Radityo Utomo, Keun-Mok Kim, Byeonghun Yun, Sang-Gug Lee, In-Young Lee:
29.7 A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL. ISSCC 2020: 452-454 - [c2]Dzuhri Radityo Utomo, Dae-Woong Park, Byeonghun Yun, Sang-Gug Lee:
A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/-3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c1]Keun-Mok Kim, Eui-Rim Jeong, Kyung-Sik Choi, Subin Kim, Byeonghun Yun, Hyunki Jung, Wonkab Oh, Jinho Ko, Sang-Gug Lee:
A 915 MHz, 499 μW, -99 dBm, and 100 kbps BFSK Direct Conversion Receiver. ESSCIRC 2019: 209-212
Coauthor Index
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