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Maurice Jamieson
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2020 – today
- 2024
- [c11]George Bisbas
, Anton Lydike
A shared compilation stack for distributed-memory parallelism in stencil DSLs. ASPLOS (3) 2024: 38-56 - [c10]Nick Brown
Performance Characterisation of the 64-Core SG2042 RISC-V CPU for HPC. ISC Workshops 2024: 354-367 - [i12]George Bisbas, Anton Lydike, Emilien Bauer, Nick Brown, Mathieu Fehr, Lawrence Mitchell, Gabriel Rodriguez-Canal, Maurice Jamieson, Paul H. J. Kelly, Michel Steuwer, Tobias Grosser:
A shared compilation stack for distributed-memory parallelism in stencil DSLs. CoRR abs/2404.02218 (2024) - [i11]Nick Brown, Maurice Jamieson:
Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC. CoRR abs/2406.12394 (2024) - 2023
- [c9]Gabriel Rodriguez-Canal
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. SC Workshops 2023: 556-565 - [c8]Nick Brown
Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. SC Workshops 2023: 904-913 - [c7]Nick Brown
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. SC Workshops 2023: 1566-1574 - [c6]Joseph K. L. Lee
Test-Driving RISC-V Vector Hardware for HPC. ISC Workshops 2023: 419-432 - [c5]Joseph K. L. Lee
Backporting RISC-V Vector Assembly. ISC Workshops 2023: 433-443 - [i10]Joseph K. L. Lee, Maurice Jamieson, Nick Brown, Ricardo Jesus:
Test-driving RISC-V Vector hardware for HPC. CoRR abs/2304.10319 (2023) - [i9]Joseph K. L. Lee, Maurice Jamieson, Nick Brown:
Backporting RISC-V Vector assembly. CoRR abs/2304.10324 (2023) - [i8]Nick Brown, Maurice Jamieson, Joseph K. L. Lee:
Experiences of running an HPC RISC-V testbed. CoRR abs/2305.00512 (2023) - [i7]Nick Brown, Maurice Jamieson, Joseph K. L. Lee, Paul Wang:
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU. CoRR abs/2309.00381 (2023) - [i6]Nick Brown, Maurice Jamieson, Anton Lydike, Emilien Bauer, Tobias Grosser
Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang. CoRR abs/2310.01882 (2023) - [i5]Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson, Emilien Bauer, Anton Lydike, Tobias Grosser
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA. CoRR abs/2310.01914 (2023) - 2022
- [c4]Maurice Jamieson
Performance of the Vipera Framework for DSLs on Micro-Core Architectures. Euro-Par Workshops 2022: 66-79 - [i4]Maurice Jamieson, Nick Brown:
Performance of the Vipera framework for DSLs on micro-core architectures. CoRR abs/2209.00894 (2022) - 2021
- [c3]Maurice Jamieson
Compact native code generation for dynamic languages on micro-core architectures. CC 2021: 131-140 - [i3]Maurice Jamieson, Nick Brown:
Compact Native Code Generation for Dynamic Languages on Micro-core Architectures. CoRR abs/2102.02109 (2021) - 2020
- [j1]Maurice Jamieson
High level programming abstractions for leveraging hierarchical memories with micro-core architectures. J. Parallel Distributed Comput. 138: 128-138 (2020) - [c2]Maurice Jamieson
Benchmarking micro-core architectures for detecting disasters at the edge. UrgentHPC@SC 2020: 27-35 - [c1]Maurice Jamieson
Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython. SciPy 2020: 107-115 - [i2]Maurice Jamieson, Nick Brown:
High level programming abstractions for leveraging hierarchical memories with micro-core architectures. CoRR abs/2010.01548 (2020) - [i1]Maurice Jamieson
Benchmarking micro-core architectures for detecting disasters at the edge. CoRR abs/2011.04983 (2020)
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