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Chih-Hsiu Lin

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2000 – 2009

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2006
[j5]
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Chih-Hsiu Lin, An-Yeu Wu, Fan-Min Li:
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 911-915 (2006)
2005
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Chih-Hsiu Lin, An-Yeu Wu:
Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(11): 2385-2396 (2005)
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Chih-Hsiu Lin, An-Yeu Wu:
Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture. IEEE Trans. Signal Process. 53(8-2): 3325-3336 (2005)
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Chih-Hsiu Lin, An-Yeu Wu:
Low cost decision feedback equalizer (DFE) design for Giga-bit systems. ICASSP (3) 2005: 1001-1004
2003
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Jen-Chih Kuo, Ching-Hua Wen, Chih-Hsiu Lin, An-Yeu Wu:
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems. EURASIP J. Adv. Signal Process. 2003(13): 1306-1316 (2003)
[j1]
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Cheng-Shing Wu, An-Yeu Wu, Chih-Hsiu Lin:
A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes. IEEE Trans. Circuits Syst. II Express Briefs 50(9): 589-601 (2003)

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