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Woo-Seok Choi
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2020 – today
- 2024
- [c34]Hyeri Roh, Woo-Seok Choi:
Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis. ISOCC 2024: 97-98 - [c33]Minjeong Kim, Taehoon Kim, Woo-Seok Choi:
Device Parameter Extraction Method for Training Performance Predicting Models. ISOCC 2024: 424-425 - 2023
- [j23]Ju-Yeon Lee, Woo-Seok Choi, Sang-Hyun Choi:
Verification and performance comparison of CNN-based algorithms for two-step helmet-wearing detection. Expert Syst. Appl. 225: 120096 (2023) - [j22]Woo-Seok Choi, Kyu-Min Shim, Kyung-Ho Chong, Jun-Eon An, Cheon-Joong Kim, Byung-Yoon Park:
Sagnac Effect Compensations and Locked States in a Ring Laser Gyroscope. Sensors 23(3): 1718 (2023) - [j21]Jiwon Shin
, Woo-Seok Choi
Phase Noise Analysis for Stochastically Injected Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2814-2818 (2023) - [j20]Hyeri Roh
A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3719-3723 (2023) - [j19]Kwang-Hoon Lee
A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4003-4007 (2023) - [c32]Daeho Yun, Minsu Park, Kahyun Kim, Kyungmin Baek, Eonhui Lee, Woo-Seok Choi, Deog-Kyoon Jeong:
A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge. A-SSCC 2023: 1-3 - [c31]Taehoon Kim, Yoona Lee, Woo-Seok Choi:
Fast Performance Evaluation Methodology for High-speed Memory Interfaces. DATE 2023: 1-6 - [c30]Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi:
A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM. ESSCIRC 2023: 273-276 - [c29]Kahyun Kim, Daeho Yun, Kyungmin Baek, Woo-Seok Choi, Deog-Kyoon Jeong:
A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation. ISCAS 2023: 1-5 - [c28]Jeongeun Song, Sunyoung Lee, Minseok Shin, Ohjun Kwon, Hansang Kim, Yujin Park, Gyubeom Hwang, Hyekyoung Jung, Hoesam Jeong, Changrock Song, Woo-Seok Choi:
A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors. ISOCC 2023: 31-32 - [c27]Jihee Kim, Woo-Seok Choi:
A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method. ISOCC 2023: 113-114 - [c26]Jia Park, Woo-Seok Choi:
An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism. ISOCC 2023: 265-266 - [c25]Taehoon Kim, Woo-Seok Choi:
Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function. ISOCC 2023: 337-338 - [c24]Hyeri Roh, Woo-Seok Choi:
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis. ISOCC 2023: 351-352 - [c23]Gi-taek An, Woo-Seok Choi, Jun-Yong Park, Kyung-Soon Lee:
JBNU at TREC 2023 Product Search Track. TREC 2023 - [i3]Hyeri Roh, Woo-Seok Choi:
Hyena: Optimizing Homomorphically Encrypted Convolution for Private CNN Inference. CoRR abs/2311.12519 (2023) - 2022
- [j18]Hyojun Kim
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits 57(6): 1712-1722 (2022) - [j17]Young-Ha Hwang
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns. IEEE J. Solid State Circuits 57(7): 2236-2249 (2022) - [j16]Woonghee Lee
Area and Power Efficient 10B6Q PAM-4 DC Balance Coder for Automotive Camera Link. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2056-2060 (2022) - [j15]Moon-Chul Choi
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2677-2681 (2022) - [j14]Daeho Yun
A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3749-3753 (2022) - [c22]Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi:
Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. AICAS 2022: 5-8 - [c21]Hanseok Kim, Woo-Seok Choi:
Improving Spiking Neural Network Accuracy Using Time-based Neurons. ISCAS 2022: 2162-2166 - [c20]Hyunjun Park, Woo-Seok Choi:
Performance Variability Modeling of Analog Circuits Using Improved Orthogonal Matching Pursuit. ISOCC 2022: 123-124 - [c19]Honggyoo Ahn, Joonghyun Song, Woo-Seok Choi:
Impact of PI Nonlinearity on High-Resolution Frequency-to-Digital Converter. ISOCC 2022: 141-142 - [c18]Jia Park, Woo-Seok Choi:
Impact of Oscillator Phase Noise on Time-Domain SNN Performance. ISOCC 2022: 364-365 - [c17]Joonghyun Song, Woo-Seok Choi:
A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion. ISOCC 2022: 398-399 - [c16]Yunhee Lee
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. VLSI Technology and Circuits 2022: 30-31 - [i2]Hanseok Kim, Woo-Seok Choi:
Improving Spiking Neural Network Accuracy Using Time-based Neurons. CoRR abs/2201.01394 (2022) - [i1]Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi:
Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons. CoRR abs/2202.02015 (2022) - 2021
- [c15]Woonghee Lee, Minkyo Shim, Yunhee Lee
0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. ESSCIRC 2021: 475-478 - 2020
- [j13]Dongwook Kim
A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 55(8): 2196-2205 (2020)
2010 – 2019
- 2019
- [j12]Dongwook Kim
A 15-Gb/s Sub-Baud-Rate Digital CDR. IEEE J. Solid State Circuits 54(3): 685-695 (2019) - [j11]Junheng Zhu
A 0.016 mm2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. IEEE J. Solid State Circuits 54(8): 2186-2194 (2019) - 2018
- [j10]Seong Joong Kim
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. IEEE J. Solid State Circuits 53(3): 814-824 (2018) - [j9]Woo-Seok Choi
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. IEEE J. Solid State Circuits 53(3): 884-895 (2018) - [c14]Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. CICC 2018: 1-4 - [c13]Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu:
A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. CICC 2018: 1-4 - [c12]Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte
Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA 2018: 561-574 - 2017
- [b1]Woo-Seok Choi:
Design of energy-efficient high-speed wireline transceiver. University of Illinois Urbana-Champaign, USA, 2017 - [j8]Saurabh Saxena
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52(5): 1399-1411 (2017) - [j7]Mrunmay Talegaonkar
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52(9): 2306-2320 (2017) - [c11]Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. CICC 2017: 1-4 - [c10]Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC 2017: 1-4 - [c9]Romesh Kumar Nandwana, Saurabh Saxena
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC 2017: 492-493 - 2016
- [j6]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 51(2): 428-439 (2016) - [c8]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC 2016: 398-399 - 2015
- [j5]Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits 50(3): 737-748 (2015) - [j4]Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits 50(4): 867-881 (2015) - [j3]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50(4): 882-895 (2015) - [c7]Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. ISSCC 2015: 1-3 - [c6]Saurabh Saxena
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC 2015: 352- - 2014
- [j2]Guanghua Shu, Saurabh Saxena
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49(4): 1036-1047 (2014) - [c5]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC 2014: 150-151 - [c4]Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC 2014: 1-2 - [c3]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC 2014: 1-2 - [c2]Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC 2014: 1-2 - 2011
- [j1]Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong:
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46(11): 2560-2570 (2011)
2000 – 2009
- 2008
- [c1]Woo-Seok Choi, Sungwon Kang, Ho-Jin Choi, Jongmoon Baik:
Automated generation of product use case scenarios in product line development. CIT 2008: 760-765
Coauthor Index
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