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Georgios C. Dogiamis
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2020 – today
- 2024
- [j3]Xibi Chen, Nathan M. Monroe, Georgios C. Dogiamis, Robert Stingel, Preston Myers, Ruonan Han:
A 265-GHz CMOS Reflectarray With 98×98 Elements for 1°-Wide Beam Forming and High-Angular-Resolution Radar Imaging. IEEE J. Solid State Circuits 59(11): 3655-3669 (2024) - 2022
- [j2]Steven Callender, Abhishek Agrawal, Amy Whitcombe, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Christopher D. Hull, Stefano Pellerano:
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. IEEE J. Solid State Circuits 57(12): 3582-3598 (2022) - [c3]Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull:
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. ISSCC 2022: 78-80 - 2021
- [j1]Xiang Yi, Cheng Wang, Zhi Hu, Jack W. Holloway, Muhammad Ibrahim Wasiq Khan, Mohamed I. Ibrahim, Mina Kim, Georgios C. Dogiamis, Bradford Perkins, Mehmet Kaynak, Rabia Tugce Yazicigil, Anantha P. Chandrakasan, Ruonan Han:
Emerging Terahertz Integrated Systems in Silicon. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3537-3550 (2021) - [c2]Jack W. Holloway, Georgios C. Dogiamis, Ruonan Han:
A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler. ISSCC 2021: 196-198 - [c1]Thomas William Brown, Georgios C. Dogiamis, Yi-Shin Yeh, Diego Correas-Serrano, Triveni S. Rane, Surej Ravikumar, Jessica C. Chou, Vijaya B. Neeli, Jose Mauricio Marulanda, Neelam Prabhu Gaunkar, Cho-Ying Lu, Iwen Huang, Ram Sadhwani, Hyung-Jin Lee, Hariprasad Chandrakumar, Jeffery W. Bates, Zinia Tuli, Qiang Yu, Mario Weiss, Jag Rangaswamy, Carlos F. Nieva, Dimitri Frolov, Telesphor Kamgaing, Ye Seul Nam, Henning Braunisch, Said Rami:
A 50 Gbps 134 GHz 16 QAM 3 m Dielectric Waveguide Transceiver System Implemented in 22nm CMOS. VLSI Circuits 2021: 1-2
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last updated on 2024-12-02 21:32 CET by the dblp team
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