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Kjell O. Jeppson
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2010 – 2019
- 2014
- [c10]Per Larsson-Edefors, Kjell O. Jeppson:
Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration. EWME 2014: 151-154 - 2013
- [c9]Kjell O. Jeppson, Per Larsson-Edefors:
Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment. MSE 2013: 48-51 - [c8]Kjell O. Jeppson:
A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4. PATMOS 2013: 39-44
2000 – 2009
- 2008
- [c7]Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson:
Noise Interaction Between Power Distribution Grids and Substrate. ISQED 2008: 84-89 - 2007
- [c6]Rashid Farivar, Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson:
Evaluation of using active circuitry for substrate noise suppression. ACM Great Lakes Symposium on VLSI 2007: 449-452 - [c5]Kjell O. Jeppson:
A Student-Oriented Course in Digital VLSI Design. MSE 2007: 57-58 - 2006
- [c4]Simon Kristiansson, Fredrik Ingvarson, Kjell O. Jeppson:
Properties and modeling of ground structures for reducing substrate noise coupling in ICs. ISCAS 2006 - 2005
- [j10]Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Nebojsa Simic, Marinel Zgrda, Kjell O. Jeppson:
A surface potential model for predicting substrate noise coupling in integrated circuits. IEEE J. Solid State Circuits 40(9): 1797-1803 (2005) - 2004
- [c3]Simon Kristiansson, Fredrik Ingvarson, Shiva Prasad Kagganti, Kjell O. Jeppson:
A surface potential model for predicting substrate noise coupling in integrated circuits. CICC 2004: 497-500
1990 – 1999
- 1996
- [j9]Kjell O. Jeppson:
Comments on the metastable behavior of mismatched CMOS latches. IEEE J. Solid State Circuits 31(2): 275-277 (1996) - 1994
- [j8]Nils Hedenstiema, Kjell O. Jeppson:
Comments on the optimum CMOS tapered buffer problem. IEEE J. Solid State Circuits 29(2): 155-158 (1994) - [j7]Kjell O. Jeppson:
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay. IEEE J. Solid State Circuits 29(6): 646-654 (1994) - 1993
- [j6]Kjell O. Jeppson, Sven Christensson, Nils Hedenstierna:
Formal definitions of edge-based geometric design rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 59-69 (1993) - [j5]Nils Hedenstierna, Kjell O. Jeppson:
Comments on 'A module generator for optimized CMOS buffers'. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 180-181 (1993) - [j4]Nils Hedenstierna, Kjell O. Jeppson:
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 265-272 (1993)
1980 – 1989
- 1989
- [c2]Nils Hedenstierna, Kjell O. Jeppson:
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. DAC 1989: 508-512 - 1988
- [j3]Nils Hedenstierna, Kjell O. Jeppson:
A corner-based hierarchical circuit extractor. Integr. 6(3): 243-261 (1988) - [c1]Nils Hedenstierna, Kjell O. Jeppson:
The use of inverse layout trees for hierarchical design verification. ICCAD 1988: 534-537 - 1987
- [j2]Nils Hedenstierna, Kjell O. Jeppson:
New algorithms for increased efficiency in hierarchical design rule checking. Integr. 5(3-4): 319-336 (1987) - [j1]Nils Hedenstierna, Kjell O. Jeppson:
CMOS Circuit Speed and Buffer Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(2): 270-281 (1987)
Coauthor Index
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