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Mahmut Yilmaz
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2020 – today
- 2024
- [c22]Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun:
A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. ITC 2024: 400-406 - 2023
- [j5]Mahmut Yilmaz
, Pavan Kumar Datla Jagannadha
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. IEEE Des. Test 40(4): 25-33 (2023) - 2022
- [c21]Seyed Nima Mozaffari, Bonita Bhaskaran, Shantanu Sarangi, Suhas M. Satheesh, Kuo Lin Fu, Nithin Valentine, P. Manikandan, Mahmut Yilmaz:
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). VTS 2022: 1-6 - [c20]Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey:
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. VTS 2022: 1-7
2010 – 2019
- 2019
- [c19]Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang:
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. VTS 2019: 1-8 - 2016
- [c18]Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian:
Advanced test methodology for complex SoCs. ITC 2016: 1-10 - [c17]Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn
Flexible scan interface architecture for complex SoCs. VTS 2016: 1-6 - [c16]Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn
Dynamic docking architecture for concurrent testing and peak power reduction. VTS 2016: 1-6 - 2014
- [p2]Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor:
Circuit Path Grading Considering Layout, Process Variations, and Cross Talk. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 95-118 - [p1]Mahmut Yilmaz:
Output Deviations-Based SDD Testing. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 119-146 - 2013
- [j4]Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults. J. Electron. Test. 29(1): 35-48 (2013) - [j3]Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1129-1142 (2013) - 2012
- [c15]Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. Asian Test Symposium 2012: 290-295 - 2011
- [j2]Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty
A Metric to Target Small-Delay Defects in Industrial Circuits. IEEE Des. Test Comput. 28(2): 52-61 (2011) - [c14]Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty
Critical Fault-Based Pattern Generation for Screening SDDs. ETS 2011: 177-182 - 2010
- [j1]Mahmut Yilmaz, Krishnendu Chakrabarty
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 760-773 (2010) - [c13]Sandeep Kumar Goel, Krishnendu Chakrabarty
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Asian Test Symposium 2010: 307-312 - [c12]Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty
A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection. Asian Test Symposium 2010: 331-336 - [c11]Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty:
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. DATE 2010: 1426-1431 - [c10]Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen:
The scan-DFT features of AMD's next-generation microprocessor core. ITC 2010: 39-48 - [c9]Alodeep Sanyal, Krishnendu Chakrabarty
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. ITC 2010: 625-634 - [c8]Ke Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty
A novel hybrid method for SDD pattern grading and selection. VTS 2010: 45-50
2000 – 2009
- 2009
- [b1]Mahmut Yilmaz:
Automated Test Grading and Pattern Selection for Small-Delay Defects. Duke University, Durham, NC, USA, 2009 - [c7]Mahmut Yilmaz, Krishnendu Chakrabarty
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects. DATE 2009: 1488-1493 - 2008
- [c6]Mahmut Yilmaz, Krishnendu Chakrabarty
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects. ITC 2008: 1-10 - [c5]Mahmut Yilmaz, Krishnendu Chakrabarty
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. VTS 2008: 233-239 - 2007
- [c4]Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin:
Lazy Error Detection for Microprocessor Functional Units. DFT 2007: 361-369 - [c3]Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz:
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor. ICCD 2007: 317-324 - 2006
- [c2]Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin:
Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier. ITC 2006: 1-10 - [c1]Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel J. Sorin, Sule Ozev:
Applying architectural vulnerability Analysis to hard faults in the microprocessor. SIGMETRICS/Performance 2006: 375-376
Coauthor Index
aka: Mohammad Tehranipoor
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