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Chin-Cheng Kuo
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2010 – 2019
- 2012
- [j5]Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai:
A fast heuristic approach for parametric yield enhancement of analog designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 35:1-35:20 (2012) - [c5]Chin-Cheng Kuo, Wei-Yi Hu, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng:
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits. DAC 2012: 1113-1118 - 2010
- [j4]Chin-Cheng Kuo, Chien-Nan Jimmy Liu:
Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 44-52 (2010) - [c4]Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu:
Behavior-level yield enhancement approach for large-scaled analog circuits. DAC 2010: 903-908
2000 – 2009
- 2009
- [j3]Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo:
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. 92-C(7): 964-972 (2009) - [j2]Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, Ching-Ji Huang:
Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1160-1172 (2009) - [c3]Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu:
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. ASP-DAC 2009: 516-521 - 2006
- [j1]Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu:
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 391-398 (2006) - [c2]Chin-Cheng Kuo, Chien-Nan Jimmy Liu:
On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. VLSI-SoC 2006: 116-121 - 2005
- [c1]Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu:
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. ACM Great Lakes Symposium on VLSI 2005: 286-290
Coauthor Index
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