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Friedel Gerfers
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2020 – today
- 2024
- [j14]Johannes Zink
, Frank Ludwig
A Multiport Coaxial Interconnection for MTCA.4 Based High-Frequency Instrumentation Applications. IEEE Trans. Instrum. Meas. 73: 1-8 (2024) - [c87]Patrick Kurth, Philipp Scholz, Philipp Nickel, Urs Hecht, Enne Wittenhagen, Kai Misselwitz, Friedel Gerfers:
A mmw Low-Noise Sub-Sampling Phase-Locked Loop with a Non-Pulsed Charge Pump, Frequency Calibration and a Compact Ultra-High-Q Resonator. ISCAS 2024: 1-5 - [c86]Kai Misselwitz, Friedel Gerfers:
A 16 GS/s Voltage-to-Time Conversion Sampler with 35.9 dB SNDR in 22 nm CMOS FDSOI. ISCAS 2024: 1-5 - [c85]Enne Wittenhagen, Dominik Wilding, Patrick Kurth, Sebastian Linnhoff, Frowin Buballa, Urs Hecht, Patrick J. Artz, Friedel Gerfers:
An 11-Bit 12 GS/s Beam-Forming Receiver ADC for a 2x2 Antenna Array utilizing True Time-Delay with 68 dBc SFDR and 55 dB SNDR. ISCAS 2024: 1-5 - 2023
- [j13]Marcel Runge
An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter. IEEE J. Solid State Circuits 58(8): 2288-2299 (2023) - [c84]Tobias Kaiser, Friedel Gerfers:
A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation. COOL CHIPS 2023: 1-6 - [c83]Urs Hecht, Helia Ordouei, Nikolay Ledentsov Jr.
True Voltage-Mode NRZ VCSEL Transmitter enabling 60 Gbit/s at 0.37 pJ/bit in 22 nm FDSOI. ESSCIRC 2023: 365-368 - [c82]Jamila Josip Borda, Friedel Gerfers:
25Gbps Automotive Ethernet: System PHY Characterization of ESD Based EM Interferences. ETFA 2023: 1-6 - [c81]Dennis Osterland, Andreas Benzin, Friedel Gerfers, Giuseppe Caire:
Undersampling and SNR Degradation in Practical Direct RF Sampling Systems. EuCNC/6G Summit 2023: 240-245 - [c80]Patrick Kurth
A Charge Pump for Sub-Sampling Phase-Locked Loops with Virtual Reference Frequency Doubling. ISCAS 2023: 1-5 - [c79]Helia Ordouei, Clirim Alija, Patrick Kurth, Friedel Gerfers:
A Digital Pre-Distortion Technique Canceling Code-and Voltage-Dependent Output Impedance Errors in Current-Steering DACs. ISCAS 2023: 1-5 - [c78]Frowin Buballa, Sebastian Linnhoff, Enne Wittenhagen, Urs Hecht, Friedel Gerfers:
A 4 GBaud 5 Vpp Class-B Pre-Driver Design for GaN-Based Switching Power Amplifier in 22 nm SOI-CMOS Utilizing LDMOS. NEWCAS 2023: 1-5 - [c77]Sebastian Linnhoff, Frowin Buballa, Julius Edler, Enne Wittenhagen, Urs Hecht, Friedel Gerfers:
A 10Bit 6 GS/s Time-Interleaved SAR ADC with a Single Full-Rate Front-End Track-and-Hold. NEWCAS 2023: 1-5 - [c76]Enne Wittenhagen, Patrick Kurth, Urs Hecht, Frowin Buballa, Sebastian Linnhoff, Nima Lotfi, Friedel Gerfers:
A 12 GS/s RF-Sampler Employing Inductive Peaking with >57 dB |THD| and >49.3 dB SNDR in 22 nm FD-SOI CMOS. NEWCAS 2023: 1-4 - [c75]Urs Hecht, Helia Ordouei, Nikolay Ledentsov Jr., Philipp Scholz, Patrick Kurth, Ilya E. Titkov, Nikolay N. Ledentsov, Friedel Gerfers:
A 0.4 pJ/bit NRZ Voltage Mode VCSEL Driver for up to 224 Gbit/s SWDM Links. OFC 2023: 1-3 - [c74]Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers:
25Gbps Automotive Ethernet ECU PCB: MDI Design Implementation and Insertion Loss Characterization. VEHITS 2023: 74-84 - [c73]Julius Edler
A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c72]Tobias Kaiser
Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA. ARCS 2022: 33-47 - [c71]Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers:
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. CICC 2022: 1-2 - [c70]Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers:
Characterization of Multi-Gigabit Automotive Ethernet Channel Radiated Emissions in Relation to ECU PCB Shield-Ground Implementations. ETFA 2022: 1-8 - [c69]Patrick Kurth
A Divider-less General PLL Lock Assist and Automatic Frequency Calibration System for Millimeter-Wave Sub-Sampling Phase-Locked Loops. ICECS 2022 2022: 1-4 - [c68]Kai Misselwitz, Marcel Runge, Friedel Gerfers:
A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC. ICECS 2022 2022: 1-4 - [c67]Enne Wittenhagen, Urs Hecht, Halil Cirit, Saman Behtash, Srinivas Venkataram, Friedel Gerfers:
A 224 Gbit/s Transceiver Front-end Design for Next Generation Data Centers. ICECS 2022 2022: 1-4 - [c66]Enne Wittenhagen, Patrick Kurth
A TI 12 GS/s Sampled Beam-Forming Receiver for a $2\times 2$ Antenna-Array with 69 dBc SFDR. ICECS 2022 2022: 1-4 - [c65]Silvio Waldmann, Helia Ordouei
A novel OFDM-based Radar and Communication System Design using Digital IQ-Modulation and 52 GS/s Direct-RF Data Converter. ISCAS 2022: 452-456 - [c64]Urs Hecht, Enne Wittenhagen, Halil Cirit, Saman Behtash, Srinivas Venkataram, Friedel Gerfers:
PAM-4/6/8 Performance and Power Analysis for Next Generation 224Gbit/s Links. ISCAS 2022: 752-756 - [c63]Helia Ordouei
In-Vehicle Network Standards - Overview and Implementation Examples. ISCAS 2022: 1023-1027 - [c62]Jamila Josip Borda, Kirsten Matheus, Friedel Gerfers:
Beyond 10Gbps Electrical Automotive Ethernet Channel Insertion Loss Characterization. IV 2022: 991-996 - [c61]Patrick J. Artz, Friedel Gerfers:
6G D-Band Receiver Model with High Spectral Efficiency Enabling Global System Optimization. MWSCAS 2022: 1-4 - [c60]Akif Omer Ucar, Friedel Gerfers:
Sturdy-MASH Delta-Sigma Modulator with Improved Resolution Using Noise-coupling Multi-bit Quantizer. MWSCAS 2022: 1-4 - 2021
- [j12]Friedel Gerfers
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 56(1): 3-6 (2021) - [j11]Suhas Shivapakash
A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. IEEE Open J. Circuits Syst. 2: 156-169 (2021) - [j10]Simon Wiedemann, Suhas Shivapakash
FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons. IEEE Open J. Circuits Syst. 2: 407-419 (2021) - [j9]Enne Wittenhagen
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 57-66 (2021) - [c59]Marcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers:
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. CICC 2021: 1-2 - [c58]Marcel Runge, Dario Schmock, Tobias Kaiser, Friedel Gerfers:
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS. CICC 2021: 1-2 - [c57]Frowin Buballa, Sebastian Linnhoff, Michael Reinhold, Friedel Gerfers:
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. ISCAS 2021: 1-5 - [c56]Patrick Kurth
A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers. ISCAS 2021: 1-5 - [c55]Sebastian Linnhoff, Erik Sippel
A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. ISCAS 2021: 1-4 - [c54]Patrick Kurth
A Divider-less Automatic Frequency Calibration for Millimeter-Wave Sub-Sampling Phase-Locked Loops. MWSCAS 2021: 718-721 - [c53]Julius Edler
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS. MWSCAS 2021: 1090-1093 - 2020
- [c52]Paul Hollmann, Marcel Runge, Friedel Gerfers:
A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network. ICECS 2020: 1-4 - [c51]Patrick Kurth
A Transmission-Line-based Phase Shifter for High-Speed, Ultra-Low-Power N-PSK Transmitters. ICECS 2020: 1-4 - [c50]Sebastian Linnhoff, Frowin Buballa, Michael Reinhold, Friedel Gerfers:
A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS. ICECS 2020: 1-4 - [c49]Tobias Kaiser, Friedel Gerfers:
Towards pW-Class IoT Nodes using Crystalline Oxide Semiconductor Dynamic Logic. ISCAS 2020: 1-5 - [c48]Marcel Runge, Dario Schmock, Enne Wittenhagen
A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX. ISCAS 2020: 1-5 - [c47]Suhas Shivapakash, Hardik Jain
A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. ISCAS 2020: 1-5 - [c46]Enne Wittenhagen
A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio. ISCAS 2020: 1-5 - [c45]Urs Hecht, Nikolay Ledentsov Jr., Lukasz Chorchos, Patrick Kurth, Nikolay N. Ledentsov, Friedel Gerfers:
Up to 30-Fold BER Improvement using a Data-Dependent FFE Switching Technique for 112Gbit/s PAM-4 VCSEL Based Links. OFC 2020: 1-3 - [c44]Nikolay N. Ledentsov, V. A. Shchukin, Vladimir P. Kalosha, Nikolay Ledentsov Jr., Lukasz Chorchos, Jaroslaw P. Turkiewicz, Urs Hecht, Patrick Kurth, Friedel Gerfers, Justin Lavrencik, Siddharth Varughese, Stephen E. Ralph:
Optical Interconnects using Single-Mode and Multi-Mode VCSEL and Multi-Mode Fiber. OFC 2020: 1-3 - [i1]Simon Wiedemann, Suhas Shivapakash, Pablo Wiedemann, Daniel Becking, Wojciech Samek, Friedel Gerfers, Thomas Wiegand:
FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4bit-Compact Multilayer Perceptrons. CoRR abs/2012.11331 (2020)
2010 – 2019
- 2019
- [c43]Norman Dodel, Roland Thewes, Anouar Laifi, Dirk Eberhardt, Stefan Keil, Leonhard Sturm, Armin Klumpp, Oliver Freudenberg, Friedel Gerfers, Gerhard Hartwich:
A CMOS-Based Electrochemical DNA Hybridization Microarray for Diagnostic Applications with 109 Test Sites. BioCAS 2019: 1-4 - [c42]Andreas Mai, Philipp Scholz, Gerhard G. Fischer, Friedel Gerfers:
High Performance Electronic Design Education - from Technology towards High Frequency Chip Sets. FIE 2019: 1-8 - [c41]Friedel Gerfers, Nima Lotfi
Body-Bias Techniques in CMOS 22FDX® for Mixed-Signal Circuits and Systems. ICECS 2019: 466-469 - [c40]Nima Lotfi
A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI. ISCAS 2019: 1-4 - [c39]Marcel Runge, Nima Lotfi
Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs. ISCAS 2019: 1-5 - [c38]Hossein Ghafarian, Helia Ordouei
Impedance Calibration Technique Canceling Process and Temperature Variation in Source Terminated DAC Drivers in 22nm FDSOI. MWSCAS 2019: 113-116 - [c37]Nima Lotfi
An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI. NEWCAS 2019: 1-4 - 2018
- [j8]Christian Schmidt
Digital-to-Analog Converters Using Frequency Interleaving: Mathematical Framework and Experimental Verification. Circuits Syst. Signal Process. 37(11): 4929-4954 (2018) - [c36]Marcel Runge, Dario Schmock, Philipp Scholz, Georg Böck, Friedel Gerfers:
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS. ESSCIRC 2018: 26-29 - [c35]Marcel Runge, Friedel Gerfers:
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. ISCAS 2018: 1-5 - [c34]Christian Schmidt
Behavioral Model for a High-Speed 2: 1 Analog Multiplexer. MWSCAS 2018: 1-4 - [c33]Helia Ordouei
Analysis of Package Impedance Effects on the Linearity of Source Series Terminated DACs. MWSCAS 2018: 250-253 - [c32]Nima Lotfi
AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs. MWSCAS 2018: 400-403 - [c31]Marcel Runge, Sebastian Linnhoff, Friedel Gerfers:
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. MWSCAS 2018: 779-782 - 2017
- [c30]Soenke Vehring, Yaoshun Ding, Dominic Maurath, Friedel Gerfers, Georg Böck:
Link-budget calculations for CMOS integrated microwave receivers. EUROCON 2017: 181-186 - [c29]Soenke Vehring, Yaoshun Ding, Philipp Scholz, Dominic Maurath, Friedel Gerfers, Georg Böck:
High output power frequency doubler for digital PLLs in fully integrated 24 GHz CMOS radar systems. ICUWB 2017: 1-4 - [c28]Hossein Ghafarian, Friedel Gerfers:
A digital calibration technique canceling non-linear switch and package impedance effects of a 1.6GS/s TX-DAC in 28 nm CMOS. ISCAS 2017: 1-4 - [c27]Marcel Runge, Friedel Gerfers:
A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters. ISCAS 2017: 1-4 - [c26]Marcel Runge, Dario Schmock, Friedel Gerfers:
Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC. MWSCAS 2017: 1025-1028 - [c25]Hossein Ghafarian, Friedel Gerfers:
Analysis and compensation technique canceling non-linear switch and package impedance effects of a 3.2GS/S TX-DAC. MWSCAS 2017: 1172-1175 - [c24]Stefanie Lehmann, Friedel Gerfers:
Channel analysis for a 6.4 Gb/s DDR5 data buffer receiver front-end. NEWCAS 2017: 109-112 - 2016
- [c23]Adel Fatemi
Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm. ISCAS 2016: 2387-2390 - 2012
- [j7]Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng:
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits 47(12): 3261-3272 (2012) - [c22]Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani:
A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC 2012: 412-413
2000 – 2009
- 2008
- [j6]Friedel Gerfers, Gerrit W. den Besten, Pavel V. Petkov, Jim E. Conder, Andreas J. Koellmann:
A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer. IEEE J. Solid State Circuits 43(6): 1436-1448 (2008) - 2007
- [j5]Matthias Keller, Alexander Buhmann, Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma-Delta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(12): 2639-2645 (2007) - 2006
- [c21]Friedel Gerfers, Maurits Ortmanns, P. Schmitz:
A transistor-based clock jitter insensitive DAC architecture. ISCAS 2006 - [c20]Pavel V. Petkov, Jim E. Conder, Friedel Gerfers:
An infinite-skew tolerant delay locked loop. ISCAS 2006 - 2005
- [j4]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(5): 875-884 (2005) - [j3]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1515-1525 (2005) - [c19]Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
A new technique for automatic error correction in Sigma-Delta modulators. ISCAS (3) 2005: 2539-2542 - [c18]Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speed. ISCAS (3) 2005: 2543-2546 - 2004
- [j2]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(6): 1088-1099 (2004) - [c17]Matthias Keller, Yiannos Manoli, Friedel Gerfers:
A calibration method for current steering digital to analog converters in continuous time multi-bit sigma delta modulators. ISCAS (1) 2004: 289-292 - [c16]Maurits Ortmanns, Markus Kuderer, Yiannos Manoli, Friedel Gerfers:
A cascaded continuous-time Sigma Delta modulator with 80 dB dynamic range. ISCAS (1) 2004: 405-408 - [c15]Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators. ISCAS (1) 2004: 1076-1079 - 2003
- [j1]Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator. IEEE J. Solid State Circuits 38(8): 1343-1352 (2003) - [c14]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback. ESSCIRC 2003: 249-252 - [c13]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
Compensation of the influence of finite gain-bandwidth on continuous-time sigma-delta modulators. ICECS 2003: 950-953 - [c12]Friedel Gerfers, Maurits Ortmanns, P. Schmitz, Yiannos Manoli, Kian Min Soh:
A clock jitter insensitive multibit DAC architecture for high-performance low-power continuous-time ΣΔ modulators. ICECS 2003: 958-961 - [c11]Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli:
A 1 V, 12-bit wideband continuous-time ΣΔ modulator for UMTS applications. ISCAS (1) 2003: 921-924 - [c10]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
Influence of finite integrator gain bandwidth on continuous-time sigma delta modulators. ISCAS (1) 2003: 925-928 - [c9]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators. ISCAS (1) 2003: 1037-1040 - 2002
- [c8]Maurits Ortmanns, Lourans Samid, Yiannos Manoli, Friedel Gerfers:
Multirate cascaded continuous time Sigma-Delta modulators. ISCAS (4) 2002: 225-228 - [c7]Friedel Gerfers, Kian Min Soh, Maurits Ortmanns, Yiannos Manoli:
Figure of merit based design strategy for low-power continuous-time Sigma-Delta modulators. ISCAS (4) 2002: 233-236 - [c6]Lourans Samid, Maurits Ortmanns, Yiannos Manoli, Friedel Gerfers:
A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator. ISCAS (3) 2002: 293-296 - 2001
- [c5]Friedel Gerfers, Yiannos Manoli:
A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters. DATE 2001: 361-369 - [c4]Maurits Ortmanns, Friedel Gerfers, Lourans Samid, Yiannos Manoli:
Successful design of cascaded continuous-time ΣΔ modulators. ICECS 2001: 321-324 - [c3]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
Clock jitter insensitive continuous-time ΣΔ modulators. ICECS 2001: 1049-1052 - [c2]Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli:
On the synthesis of cascaded continuous-time Sigma-Delta modulators. ISCAS (5) 2001: 419-422 - 2000
- [c1]Friedel Gerfers, Yiannos Manoli:
A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). ISLPED 2000: 219-221
Coauthor Index
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