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Kartik Mohanram
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2010 – 2019
- 2019
- [c68]Shivam Swami, Kartik Mohanram:
ASSET: Architectures for Smart Security of Non-Volatile Memories. ISVLSI 2019: 348-353 - 2018
- [j18]Joydeep Rakshit
, Kartik Mohanram:
LEO: Low Overhead Encryption ORAM for Non-Volatile Memories. IEEE Comput. Archit. Lett. 17(2): 100-104 (2018) - [j17]Shivam Swami
ARSENAL: Architecture for Secure Non-Volatile Memories. IEEE Comput. Archit. Lett. 17(2): 192-196 (2018) - [j16]Ali Alsuwaiyan, Kartik Mohanram:
MFNW: An MLC/TLC Flip-N-Write Architecture. ACM J. Emerg. Technol. Comput. Syst. 14(2): 28:1-28:32 (2018) - [c67]Shivam Swami, Joydeep Rakshit, Kartik Mohanram:
STASH: security architecture for smart hybrid memories. DAC 2018: 85:1-85:6 - [c66]Shivam Swami, Kartik Mohanram:
ACME: advanced counter mode encryption for secure non-volatile memories. DAC 2018: 86:1-86:6 - [c65]Poovaiah M. Palangappa, Kartik Mohanram:
CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. DAC 2018: 87:1-87:6 - [c64]Shivam Swami, Kartik Mohanram:
ADAM: Architecture for write disturbance mitigation in scaled phase change memory. DATE 2018: 1235-1240 - [c63]Poovaiah M. Palangappa, Kartik Mohanram:
RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs. ICCAD 2018: 67 - [c62]Joydeep Rakshit, Kartik Mohanram:
ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories. ICCD 2018: 100-107 - 2017
- [j15]Shivam Swami
Reliable Nonvolatile Memories: Techniques and Measures. IEEE Des. Test 34(3): 31-41 (2017) - [j14]Poovaiah M. Palangappa, Kartik Mohanram:
CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs. ACM Trans. Archit. Code Optim. 14(1): 10:1-10:30 (2017) - [j13]Shivam Swami, Poovaiah M. Palangappa, Kartik Mohanram:
ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories. ACM Trans. Archit. Code Optim. 14(4): 40:1-40:29 (2017) - [c61]Joydeep Rakshit
ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories. DAC 2017: 11:1-11:6 - [c60]Shivam Swami, Kartik Mohanram:
COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories. DATE 2017: 906-909 - [c59]Ali Alsuwaiyan, Kartik Mohanram:
L3EP: Low latency, low energy program-and-verify for triple-level cell phase change memory. NANOARCH 2017: 27-32 - [c58]Jiayin Li, Kartik Mohanram:
Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies. VLSID 2017: 47-52 - 2016
- [j12]Joydeep Rakshit
Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems. ACM J. Emerg. Technol. Comput. Syst. 13(2): 18:1-18:28 (2016) - [j11]Poovaiah M. Palangappa, Jiayin Li, Kartik Mohanram:
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory. IEEE Trans. Computers 65(4): 1025-1040 (2016) - [c57]Shivam Swami, Joydeep Rakshit
SECRET: smartly EnCRypted energy efficient non-volatile memories. DAC 2016: 166:1-166:6 - [c56]Ali Alsuwaiyan, Kartik Mohanram:
An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories. ACM Great Lakes Symposium on VLSI 2016: 403-408 - [c55]Poovaiah M. Palangappa, Kartik Mohanram:
CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM. HPCA 2016: 90-101 - [c54]Shivam Swami, Kartik Mohanram:
E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories. VLSID 2016: 373-378 - 2015
- [j10]Jiayin Li, David B. Dgien, Nathan Altay Hunter, Yirong Zhao, Kartik Mohanram:
Two-Port PCM Architecture for Network Processing. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2135-2148 (2015) - [c53]Joydeep Rakshit
Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design. DAC 2015: 143:1-143:6 - [c52]Poovaiah M. Palangappa, Kartik Mohanram:
Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories. ACM Great Lakes Symposium on VLSI 2015: 221-224 - [c51]Ali Alsuwaiyan, Kartik Mohanram:
MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories. NANOARCH 2015: 13-18 - 2014
- [j9]Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram:
Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE Trans. Computers 63(2): 497-509 (2014) - [c50]Jiayin Li, Kartik Mohanram:
Write-once-memory-code phase change memory. DATE 2014: 1-6 - [c49]David B. Dgien, Poovaiah M. Palangappa, Nathan Altay Hunter, Jiayin Li, Kartik Mohanram:
Compression architecture for bit-write reduction in non-volatile memory technologies. NANOARCH 2014: 51-56 - 2013
- [j8]Mihir R. Choudhury, Kartik Mohanram:
Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1163-1176 (2013) - [c48]Kartik Mohanram, Matthew Wartell, Sundar Iyer:
Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification. DATE 2013: 1490-1493 - [c47]Yirong Zhao, Jiayin Li, Kartik Mohanram:
Multi-port FinFET SRAM design. ACM Great Lakes Symposium on VLSI 2013: 293-298 - 2012
- [c46]Kai Du, Peter J. Varman, Kartik Mohanram:
High performance reliable variable latency carry select addition. DATE 2012: 1257-1262 - [c45]Kartik Mohanram, Xuebei Yang, Masoud Rostami, Guanxiong Liu, Alexander A. Balandin:
Ambipolar circuits for analog, mixed-signal, and radio-frequency applications. NANOARCH 2012: 1-6 - 2011
- [j7]M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 242-255 (2011) - [j6]Masoud Rostami, Kartik Mohanram:
Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 337-349 (2011) - [c44]Andrew Zukoski, Xuebei Yang, Kartik Mohanram:
Universal logic modules based on double-gate carbon nanotube transistors. DAC 2011: 884-889 - [c43]Xuebei Yang, Kartik Mohanram:
Robust 6T Si tunneling transistor SRAM design. DATE 2011: 740-745 - [c42]Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram:
Reliability-driven don't care assignment for logic synthesis. DATE 2011: 1560-1565 - [c41]Xuebei Yang, Kartik Mohanram:
Unequal-error-protection codes in SRAMs for mobile multimedia applications. ICCAD 2011: 21-27 - [c40]Kai Du, Peter J. Varman
Static window addition: A new paradigm for the design of variable latency adders. ICCD 2011: 455-456 - 2010
- [c39]Masoud Rostami, Kartik Mohanram:
Novel dual-Vth independent-gate FinFET circuits. ASP-DAC 2010: 867-872 - [c38]M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
Power consumption of logic circuits in ambipolar carbon nanotube technology. DATE 2010: 303-306 - [c37]Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
Analytical model for TDDB-based performance degradation in combinational logic. DATE 2010: 423-428 - [c36]Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
TIMBER: Time borrowing and error relaying for online timing error resilience. DATE 2010: 1554-1559 - [c35]Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram:
Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI 2010: 173-178 - [c34]Xuebei Yang, Gianluca Fiori
Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. ACM Great Lakes Symposium on VLSI 2010: 233-238 - [c33]Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram:
Graphene tunneling FET and its applications in low-power circuit design. ACM Great Lakes Symposium on VLSI 2010: 263-268 - [c32]Mihir R. Choudhury, Kartik Mohanram:
Bi-decomposition of large Boolean functions using blocking edge graphs. ICCAD 2010: 586-591
2000 – 2009
- 2009
- [j5]Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Giovanni De Micheli, Ioannis Xenarios
Modeling stochasticity and robustness in gene regulatory networks. Bioinform. 25(12) (2009) - [j4]Mihir R. Choudhury, Quming Zhou, Kartik Mohanram:
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J. Electron. Test. 25(2-3): 197-207 (2009) - [j3]Mihir R. Choudhury, Kartik Mohanram:
Reliability Analysis of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 392-405 (2009) - [c31]Mihir R. Choudhury, Kartik Mohanram:
Timing-driven optimization using lookahead logic circuits. DAC 2009: 390-395 - [c30]Mihir R. Choudhury, Kartik Mohanram:
Masking timing errors on speed-paths in logic circuits. DATE 2009: 87-92 - [c29]M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. DATE 2009: 622-627 - 2008
- [c28]Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram:
Technology exploration for graphene nanoribbon FETs. DAC 2008: 272-277 - [c27]Mihir R. Choudhury, Kartik Mohanram:
Approximate logic circuits for low overhead, non-intrusive concurrent error detection. DATE 2008: 903-908 - [c26]Kartik Mohanram:
Error Detection and Tolerance for Scaled Electronic Technologies. DFT 2008: 83-83 - [c25]Quming Zhou, Mihir R. Choudhury, Kartik Mohanram:
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. ETS 2008: 179-184 - [c24]Kartik Mohanram, Jing Guo:
Graphene nanoribbon FETs: technology exploration and CAD. ICCAD 2008: 412-415 - 2007
- [c23]Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram:
Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. DATE 2007: 1072-1077 - [c22]Mihir R. Choudhury, Kartik Mohanram:
Accurate and scalable reliability analysis of logic circuits. DATE 2007: 1454-1459 - [c21]Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen:
Parallel domain decomposition for simulation of large-scale power grids. ICCAD 2007: 54-59 - [c20]Quming Zhou, Lin Zhong, Kartik Mohanram:
Power signal processing: a new perspective for power analysis and optimization. ISLPED 2007: 165-170 - [c19]Mosin Mondal, Kartik Mohanram, Yehia Massoud:
Parameter-Variation-Aware Analysis for Noise Robustness. ISQED 2007: 655-659 - 2006
- [j2]Quming Zhou, Kartik Mohanram:
Gate sizing to radiation harden combinational logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 155-166 (2006) - [c18]Alan L. Cox, Kartik Mohanram, Scott Rixner:
Dependable != unaffordable. ASID 2006: 58-62 - [c17]Quming Zhou, Kartik Mohanram:
Elmore model for energy estimation in RC trees. DAC 2006: 965-970 - [c16]Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen:
Large power grid analysis using domain decomposition. DATE 2006: 27-32 - [c15]Mihir R. Choudhury, Quming Zhou, Kartik Mohanram:
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ICCAD 2006: 204-209 - [c14]Quming Zhou, Mihir R. Choudhury, Kartik Mohanram:
Design Optimization for Robustness to Single Event Upsets. VTS 2006: 202-207 - 2005
- [c13]Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas:
Structure preserving reduction of frequency-dependent interconnect. DAC 2005: 939-942 - [c12]Kartik Mohanram:
Simulation of transients caused by single-event upsets in combinational logic. ITC 2005: 9 - [c11]Kartik Mohanram:
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. VTS 2005: 327-333 - 2004
- [j1]Kartik Mohanram, Nur A. Touba:
Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1234-1243 (2004) - [c10]Quming Zhou, Kartik Mohanram:
Cost-effective radiation hardening technique for combinational logic. ICCAD 2004: 100-106 - [c9]Quming Zhou, Kartik Mohanram:
Analysis of delay caused by bridging faults in RLC interconnects. ITC 2004: 1044-1052 - [c8]Kartik Mohanram, Scott Rixner:
Context-Independent Codes for Off-Chip Interconnects. PACS 2004: 107-119 - 2003
- [c7]Kartik Mohanram, Nur A. Touba:
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT 2003: 433- - [c6]Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba:
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. IOLTS 2003: 35- - [c5]Kartik Mohanram, Nur A. Touba:
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC 2003: 893-901 - [c4]Kartik Mohanram, Nur A. Touba:
Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS 2003: 121-127 - 2002
- [c3]Kartik Mohanram, Nur A. Touba:
Input Ordering in Concurrent Checkers to Reduce Power Consumption. DFT 2002: 87-98 - [c2]Kartik Mohanram, C. V. Krishna, Nur A. Touba:
A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. ISCAS (1) 2002: 577-580
1990 – 1999
- 1999
- [c1]Abhijit Jas, Kartik Mohanram, Nur A. Touba:
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275-
Coauthor Index
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