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Eric Liau
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2000 – 2009
- 2008
- [c8]Thomas Nirmaier, Jose Torres Zaguirre, Eric Liau, Wolfgang Spirkl, Armin Rettenberger, Doris Schmitt-Landsiedel:
Efficient High-Speed Interface Verification and Fault Analysis. ITC 2008: 1-9 - 2007
- [i1]Eric Liau, Doris Schmitt-Landsiedel:
Computational Intelligence Characterization Method of Semiconductor Device. CoRR abs/0710.4734 (2007) - 2006
- [c7]Thomas Janik, Eric Liau, Harald Lorenz, Manfred Menke, Eckehard Plaettner, Joerg Schweden, Helmut Seitz, Esther Vega-Ordonez:
A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation. ISCAS 2006 - [c6]Eric Liau Chee Hong, Manfred Menke, Thomas Janik, Doris Schmitt-Landsiedel:
Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing. ITC 2006: 1-10 - [c5]Thomas Nirmaier, Wolfgang Spirkl, Eric Liau Chee Hong:
Fully automated semiconductor operating condition testing. ITC 2006: 1-9 - 2005
- [c4]Eric Liau, Doris Schmitt-Landsiedel:
Computational Intelligence Characterization Method of Semiconductor Device. DATE 2005: 456-461 - [c3]Eric Liau, Doris Schmitt-Landsiedel:
Computational intelligence based testing for semiconductor measurement systems. ITC 2005: 10 - 2003
- [c2]Eric Liau, Doris Schmitt-Landsiedel:
Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. ETW 2003: 105-110 - [c1]Eric Liau, Doris Schmitt-Landsiedel:
Evolution of automatic semiconductor test equipment: automatic test pattern learning, classification, optimisation and generation for power supply noise. VECIMS 2003: 39-44
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