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Viresh Paruthi
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2020 – today
- 2024
- [c16]Prashanth Vijayaraghavan
, Apoorva Nitsure
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization. MLCAD 2024: 28:1-28:10
2010 – 2019
- 2015
- [j4]Klaus-Dieter Schubert, John M. Ludden, Salma Ayub, J. Behrend, Bishop Brock, Fady Copty, S. M. German, Oz Hershkovitz, H. Horbach, Jonathan R. Jackson, K. Keuerleber, J. Koesters, Larry S. Leitner, G. B. Meil, Charles Meissner, Ronny Morad, Amir Nahir, Viresh Paruthi, Richard D. Peterson, Randall R. Pratt, Michal Rimon, John Schumann:
Solutions to IBM POWER8 verification challenges. IBM J. Res. Dev. 59(1) (2015) - [c15]Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru:
Designer-level verification: an industrial experience story. DATE 2015: 410-411 - 2014
- [j3]Alexey Lvov, Luis Alfonso Lastras-Montaño, Barry M. Trager, Viresh Paruthi, Robert Shadowen, Ali El-Zein:
Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry. Formal Methods Syst. Des. 45(2): 189-212 (2014) - [c14]Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky:
Automatic Verification of Floating Point Units. DAC 2014: 151:1-151:6 - 2012
- [c13]Alexey Lvov, Luis Alfonso Lastras-Montaño, Viresh Paruthi, Robert Shadowen, Ali El-Zein:
Formal verification of error correcting circuits using computational algebraic geometry. FMCAD 2012: 141-148 - 2011
- [c12]Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony:
Hybrid verification of a hardware modular reduction engine. FMCAD 2011: 207-214 - 2010
- [c11]Gadiel Auerbach, Fady Copty, Viresh Paruthi:
Formal verification of arbiters using property strengthening and underapproximations. FMCAD 2010: 21-24 - [c10]Viresh Paruthi:
Large-scale application of formal verification: From fiction to fact. FMCAD 2010: 175-180
2000 – 2009
- 2009
- [c9]Krishnan Kailas, Viresh Paruthi, Brian Monwai:
Formal verification of correctness and performance of random priority-based arbiters. FMCAD 2009: 101-107 - 2006
- [c8]Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen:
Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . ICCD 2006: 259-266 - 2005
- [c7]Viresh Paruthi, Christian Jacobi, Kai Weber:
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. CHARME 2005: 114-128 - [c6]Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman:
Exploiting suspected redundancy without proving it. DAC 2005: 463-466 - [c5]Christian Jacobi, Kai Weber, Viresh Paruthi, Jason Baumgartner:
Automatic Formal Verification of Fused-Multiply-Add FPUs. DATE 2005: 1298-1303 - 2004
- [c4]Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann:
Scalable Automated Verification via Expert-System Guided Transformations. FMCAD 2004: 159-173 - 2002
- [j2]John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile:
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. IBM J. Res. Dev. 46(1): 53-76 (2002) - [j1]Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai:
Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1377-1394 (2002) - 2001
- [c3]Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi:
Circuit-based Boolean Reasoning. DAC 2001: 232-237 - 2000
- [c2]Viresh Paruthi, Andreas Kuehlmann:
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. ICCD 2000: 459-464
1990 – 1999
- 1998
- [c1]Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri:
Automatic data path abstraction for verification of large scale designs. ICCD 1998: 192-194
Coauthor Index
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