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Muralidhar Talupur
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2010 – 2019
- 2018
- [p1]Parosh Aziz Abdulla, A. Prasad Sistla, Muralidhar Talupur:
Model Checking Parameterized Systems. Handbook of Model Checking 2018: 685-725 - 2016
- [j3]Divjyot Sethi, Muralidhar Talupur, Sharad Malik
:
Model checking unbounded concurrent lists. Int. J. Softw. Tools Technol. Transf. 18(4): 375-391 (2016) - [e1]Ruzica Piskac, Muralidhar Talupur:
2016 Formal Methods in Computer-Aided Design, FMCAD 2016, Mountain View, CA, USA, October 3-6, 2016. IEEE 2016, ISBN 978-0-9835678-6-8 [contents] - 2014
- [c15]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. ATVA 2014: 330-347 - [i1]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. CoRR abs/1407.7468 (2014) - 2013
- [c14]Divjyot Sethi, Muralidhar Talupur, Sharad Malik:
Model Checking Unbounded Concurrent Lists. SPIN 2013: 320-340 - 2012
- [c13]Divjyot Sethi, Muralidhar Talupur, Daniel Schwartz-Narbonne, Sharad Malik:
Parameterized Model Checking of Fine Grained Concurrency. SPIN 2012: 208-226 - 2011
- [c12]Muralidhar Talupur:
Hardware model checking: status, challenges, and opportunities. FMCAD 2011: 154 - [c11]Muralidhar Talupur, Hyojung Han:
Biased Model Checking Using Flows. TACAS 2011: 239-253
2000 – 2009
- 2008
- [c10]Edmund M. Clarke, Muralidhar Talupur, Helmut Veith:
Proving Ptolemy Right: The Environment Abstraction Framework for Model Checking Concurrent Systems. TACAS 2008: 33-47 - 2007
- [j2]Malay K. Ganai, Muralidhar Talupur, Aarti Gupta
SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic. J. Satisf. Boolean Model. Comput. 3(1-2): 91-114 (2007) - 2006
- [c9]Kamala Krithivasan, Prahladh Harsha, Muralidhar Talupur:
Communicating Distributed H systems with Simple Splicing Rules. CDES 2006: 107-111 - [c8]Malay K. Ganai, Muralidhar Talupur, Aarti Gupta:
SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver. TACAS 2006: 135-150 - [c7]Edmund M. Clarke, Muralidhar Talupur, Helmut Veith:
Environment Abstraction for Parameterized Verification. VMCAI 2006: 126-141 - 2004
- [c6]Muralidhar Talupur, Nishant Sinha, Ofer Strichman
Range Allocation for Separation Logic. CAV 2004: 148-161 - [c5]Edmund M. Clarke, Muralidhar Talupur, Tayssir Touili, Helmut Veith:
Verification by Network Decomposition. CONCUR 2004: 276-291 - [c4]Shuvendu K. Lahiri, Randal E. Bryant, Amit Goel, Muralidhar Talupur:
Revisiting Positive Equality. TACAS 2004: 1-15 - 2003
- [c3]Edmund M. Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang:
Making Predicate Abstraction Efficient: How to Eliminate Redundant Predicates. CAV 2003: 126-140 - [c2]Edmund M. Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang:
High Level Verification of Control Intensive Systems Using Predicate Abstraction. MEMOCODE 2003: 55-64 - [c1]Edmund M. Clarke, Muralidhar Talupur, Helmut Veith, Dong Wang:
SAT Based Predicate Abstraction for Hardware Verification. SAT 2003: 78-92 - 2000
- [j1]Lakshminarayanan Subramanian, Muralidhar Talupur, Kamala Krithivasan, C. Pandu Rangan:
On the Generative Power of Simple H Systems. J. Autom. Lang. Comb. 5(4): 457-473 (2000)
Coauthor Index
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