default search action
Kostas Masselos
Konstantinos Masselos
Person information
- affiliation: Imperial College London, UK
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [j33]Pantelis Koutroumpis, Konstantinos Masselos:
Tower Companies vs. Mergers in Mobile Networks. IEEE Commun. Mag. 62(11): 68-74 (2024) - 2023
- [j32]Pantelis Koutroumpis, Konstantinos Masselos, Dimitris Varoutas:
Editorial: Infrastructure sharing in broadband networks: impact on telecommunications operators and consumers. Frontiers Comput. Sci. 5 (2023) - [j31]Chris Karanikolas
, Grigoris Dimitroulakos
Simulating Software Evolution to Evaluate the Reliability of Early Decision-making among Design Alternatives toward Maintainability. ACM Trans. Softw. Eng. Methodol. 32(3): 70:1-70:38 (2023) - 2020
- [j30]Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor:
A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism. ACM Trans. Embed. Comput. Syst. 19(6): 50:1-50:27 (2020) - [j29]Christakis Lezos, Grigoris Dimitroulakos, Ioannis Latifis, Konstantinos Masselos:
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis. ACM Trans. Design Autom. Electr. Syst. 25(6): 51:1-51:26 (2020) - [d1]Chris Karanikolas
Experimental (raw) Data of Statistical Comparison Between Formal and Simulated Models' Outcomes for CIBI vs. CVP General Problem. IEEE DataPort, 2020
2010 – 2019
- 2017
- [j28]Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor:
A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors. ACM Trans. Design Autom. Electr. Syst. 22(2): 32:1-32:28 (2017) - [j27]Chris Karanikolas
Early Evaluation of Implementation Alternatives of Composite Data Structures Toward Maintainability. ACM Trans. Softw. Eng. Methodol. 26(2): 8:1-8:44 (2017) - 2016
- [c50]Christakis Lezos, Grigoris Dimitroulakos, Ioannis Latifis, Konstantinos Masselos:
Automatic Generation of Code Analysis Tools: The CastQL Approach. RWDSL@CGO 2016: 3:1-3:10 - [c49]Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor:
Matlab to C compilation targeting Application Specific Instruction Set Processors. DATE 2016: 1453-1456 - [c48]Christakis Lezos, Ioannis Latifis, Grigoris Dimitroulakos, Konstantinos Masselos:
Compiler-Directed Data Locality Optimization in MATLAB. SCOPES 2016: 6-9 - 2015
- [c47]Christakis Lezos, Grigoris Dimitroulakos, Konstantinos Masselos:
Reuse distance analysis for locality optimization in loop-dominated applications. DATE 2015: 1237-1240 - 2014
- [j26]Theodoros Lioris, Grigoris Dimitroulakos, Konstantinos Masselos:
An early memory hierarchy evaluation simulator for multimedia applications. Microprocess. Microsystems 38(1): 31-41 (2014) - [c46]Vasiliki Giannakopoulou, Kostas Masselos:
Hardware architecture for Fast 2D distance transformations. ICDIP 2014: 91591X - 2013
- [j25]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker
Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsystems 37(8-C): 1033-1049 (2013) - [c45]Christakis Lezos, Grigoris Dimitroulakos, Angeliki Freskou, Konstantinos Masselos:
Dynamic source code analysis for memory hierarchy optimization in multimedia applications. DASIP 2013: 343-344 - [c44]Nikolaos Kavvadias, Kostas Masselos:
The HercuLeS high-level synthesis environment. FPL 2013: 1 - [c43]Nikolaos Kavvadias, Kostas Masselos:
Hardware design space exploration using HercuLeS HLS. Panhellenic Conference on Informatics 2013: 195-202 - 2012
- [c42]Nikolaos Kavvadias, Kostas Masselos:
Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation. ASAP 2012: 157-160 - [c41]Nikolaos Kavvadias, Kostas Masselos:
Design of fixed-point rounding operators for the VHDL-2008 standard. DASIP 2012: 1-8 - [c40]Grigoris Dimitroulakos, Christakis Lezos, Konstantinos Masselos:
MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations. DASIP 2012: 385-386 - [c39]Grigoris Dimitroulakos, Theodoros Lioris, Christakis Lezos, Konstantinos Masselos:
XMSIM: A tool for early memory hierarchy evaluation. DASIP 2012: 405-406 - [c38]Jürgen Becker
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD 2012: 114-121 - [c37]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC 2012: 1-8 - [c36]George Goulas, Panayiotis Alefragis
From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS 2012: 268-275 - 2011
- [j24]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54(1): 1-10 (2011) - [e1]Nikolaos S. Voros, Amar Mukherjee, Nicolas Sklavos, Konstantinos Masselos, Michael Hübner:
VLSI 2010 Annual Symposium - Selected papers. Lecture Notes in Electrical Engineering 105, Springer 2011, ISBN 978-94-007-1487-8 [contents] - 2010
- [c35]Nikolaos Kavvadias, Konstantinos Masselos:
Efficient Hardware Looping Units for FPGAs. ISVLSI 2010: 35-40 - [c34]Theodoros Lioris, Grigoris Dimitroulakos, Kostas Masselos:
XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluation. ISVLSI (Selected papers) 2010: 199-216 - [c33]Theodoros Lioris, Grigoris Dimitroulakos, Kostas Masselos:
XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation. ISVLSI 2010: 375-380 - [c32]Georgia Kalogeridou, Nikolaos S. Voros
System Level Design of Complex Hardware Applications Using ImpulseC. ISVLSI 2010: 473-474
2000 – 2009
- 2009
- [j23]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Comput. Digit. Tech. 3(3): 235-246 (2009) - [j22]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 305-315 (2009) - 2008
- [j21]Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung:
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1268-1280 (2008) - [j20]Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. J. Signal Process. Syst. 51(1): 3-21 (2008) - [c31]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. 2008: 295-304 - [c30]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184 - [c29]Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos:
Co-optimisation of datapath and memory in outer loop pipelining. FPT 2008: 1-8 - 2007
- [j19]Konstantinos Masselos, Nikolaos S. Voros
Implementation of Wireless Communications Systems on FPGA-Based Platforms. EURASIP J. Embed. Syst. 2007 (2007) - [c28]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260 - [c27]Nikos S. Voros
Prototyping of a WLAN system using C++ based architecture exploration. MobiMedia 2007: 54 - 2006
- [c26]Konstantinos Masselos, George A. Constantinides, Qiang Liu:
Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. FPL 2006: 1-6 - [c25]Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo:
System Level Architecture Exploration for Reconfigurable Systems On Chip. FPL 2006: 1-6 - [c24]Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong
FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. FPL 2006: 1-6 - [c23]Maria E. Angelopoulou, Konstantinos Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. FPT 2006: 181-188 - [c22]Kostas Masselos, Yiannis Andreopoulos, Thanos Stouraitis:
Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP. ISCAS 2006 - 2004
- [j18]Nikolaos S. Voros
Embedded System Design Using Formal Model Refinement: An Approach Based on the Combined Use of UML and the B Language. Des. Autom. Embed. Syst. 9(2): 67-99 (2004) - [j17]Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man:
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors. J. VLSI Signal Process. 37(1): 53-73 (2004) - [c21]Kari Tiensyrjä, Miroslav Cupák, Kostas Masselos, Marko Pettissalo:
SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip. FDL 2004: 428-440 - [c20]Yang Qu, Kari Tiensyrjä, Kostas Masselos:
System-Level Modeling of Dynamically Reconfigurable Co-processors. FPL 2004: 881-885 - [c19]Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis:
A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624 - [c18]Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis:
Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. PATMOS 2004: 613-622 - 2003
- [j16]Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man:
Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications. Des. Autom. Embed. Syst. 8(1): 51-86 (2003) - [j15]Kostas Masselos, Antti Pelkonen, Miroslav Cupák, Spyros Blionas:
Realization of wireless multimedia communication systems on reconfigurable platforms. J. Syst. Archit. 49(4-6): 155-175 (2003) - [j14]Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis
Power efficient data path synthesis of sum-of-products computations. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 446-450 (2003) - [j13]Yiannis Andreopoulos, Peter Schelkens
High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations. J. VLSI Signal Process. 34(3): 209-226 (2003) - [c17]Antti Pelkonen, Kostas Masselos, Miroslav Cupák:
System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC. IPDPS 2003: 174 - [c16]Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas:
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439 - 2002
- [j12]Konstantinos Masselos, Spyros Theoharis, Panagiotis Merakos, Thanos Stouraitis
Memory accesses reordering for interconnect power reduction in sum-of-products computations. IEEE Trans. Signal Process. 50(11): 2889-2899 (2002) - [j11]Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man:
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 515-518 (2002) - [j10]Panagiotis K. Merakos, Konstantinos Masselos, Constantinos E. Goutis:
Power Efficient Hierarchical Scheduling for DSP Transformations. VLSI Design 14(2): 203-217 (2002) - [j9]Nikolaos D. Zervas, Konstantinos Masselos, Yorgos A. Karayiannis, Costas E. Goutis:
Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores. VLSI Design 14(3): 273-286 (2002) - [c15]George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis:
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036 - [c14]Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, Aristodemos Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas:
A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. FPL 2002: 1080-1083 - [c13]Yiannis Andreopoulos, Kostas Masselos, Peter Schelkens
Cache misses and energy-dissipation results for JPEG-2000 filtering. DSP 2002: 201-209 - [c12]Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis:
Power Efficient Vector Quantization Design Using Pixel Truncation. PATMOS 2002: 409-418 - 2001
- [c11]Kostas Masselos, Francky Catthoor, A. Kakarudas, Costas E. Goutis, Hugo De Man:
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures. ICECS 2001: 285-288 - 2000
- [b1]Konstantinos Masselos:
Υψηλού επιπέδου μέθοδοι μείωσης της κατανάλωσης ενέργειας σε εφαρμογές πολυμέσων. University of Patras, Greece, 2000 - [j8]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power architectures for digital signal processing. J. Syst. Archit. 46(7): 551-571 (2000) - [j7]Kostas Masselos, Koen Danckaert, Francky Catthoor, Nikolaos D. Zervas, Constantinos E. Goutis, Hugo De Man:
A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints. J. VLSI Signal Process. 26(3): 291-317 (2000) - [c10]Kostas Masselos, Yorgos A. Karayiannis, I. Andreopoulos, Thanos Stouraitis
Development of a power efficient image coding algorithm based on integer wavelet transform. ICECS 2000: 457-460 - [c9]Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power synthesis of sum-of-products computation (poster session). ISLPED 2000: 234-237
1990 – 1999
- 1999
- [j6]Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man:
Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec. J. Syst. Archit. 45(10): 791-808 (1999) - [j5]Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis:
Strategy for power-efficient design of parallel systems. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 258-265 (1999) - [j4]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis
Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 492-497 (1999) - [j3]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis. VLSI Design 10(2): 177-202 (1999) - [c8]Kostas Masselos, Francky Catthoor, Costas E. Goutis, H. DeMan:
System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors. ICECS 1999: 1733-1736 - [c7]Nikolaos D. Zervas, Kostas Masselos, Odysseas G. Koufopavlou, Constantinos E. Goutis:
Power exploration of multimedia applications realized on embedded cores. ISCAS (4) 1999: 378-381 - [c6]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power synthesis of sum-of-product computation in DSP algorithms. ISCAS (6) 1999: 420-423 - [c5]Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man:
A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. ISLPED 1999: 270-272 - 1998
- [j2]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis
A novel algorithm for low-power image and video coding. IEEE Trans. Circuits Syst. Video Technol. 8(3): 258-263 (1998) - [j1]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Trade-Off Analysis of a Low-Power Image Coding Algorithm. J. VLSI Signal Process. 18(1): 65-80 (1998) - [c4]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low-power implementation of discrete wavelet transform. EUSIPCO 1998: 1-4 - [c3]Konstantinos Masselos, Thanos Stouraitis, Costas E. Goutis:
Novel codebook generation algorithms for vector quantization image compression. ICASSP 1998: 2661-2664 - 1996
- [c2]Kostas Masselos, Konstantina Karagianni, Yorgos A. Karayiannis, Thanos Stouraitis:
A parallel image compression scheme based on fractal coding and vector quantization. ICECS 1996: 712-715 - [c1]Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis:
Low-power image decoding using fractals. ICECS 1996: 748-751
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-25 22:45 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: