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"A High Reliability FPGA Chip Identification Generator Based on PDLs."

Kai Zhou et al. (2018)

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DOI: 10.1109/ATS.2018.00023

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/ats/ZhouLJHYXY18
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  persistent URL:
  - https://dblp.org/rec/conf/ats/ZhouLJHYXY18
Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao:
A High Reliability FPGA Chip Identification Generator Based on PDLs. ATS 2018: 63-67

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