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"A gate level model for CMOS combinational logic circuits with application ..."

Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain (1984)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2012-03-01

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  dblp key:
  - conf/dac/ReddyAJ84
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  persistent URL:
  - https://dblp.org/rec/conf/dac/ReddyAJ84
Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain:
A gate level model for CMOS combinational logic circuits with application to fault detection. DAC 1984: 504-509

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