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"A 2-20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay ..."

Yinghao Chen et al. (2024)

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DOI: 10.1007/S00034-023-02473-5

access: closed

type: Journal Article

metadata version: 2024-01-22

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  dblp key:
  - journals/cssp/ChenCFZZH24
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  - https://dblp.org/rec/journals/cssp/ChenCFZZH24
Yinghao Chen, Yingmei Chen, Wentian Fan, Qingyi Zhao, En Zhu, Zhengfei Hu:
A 2-20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop. Circuits Syst. Signal Process. 43(1): 318-330 (2024)

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