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"Verification and Validation with Prototype Chip Implemented with Layout ..."

Hiroshi Iwata, Kokoro Yamasaki, Ken-ichi Yamaguchi (2024)

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DOI: 10.1007/S10836-024-06128-4

access: closed

type: Journal Article

metadata version: 2024-11-06

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Hiroshi Iwata, Kokoro Yamasaki, Ken-ichi Yamaguchi:
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements. J. Electron. Test. 40(4): 497-508 (2024)

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