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"A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size ..."
Liang Hong et al. (2013)
- Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao:
A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electron. Express 10(9): 20130210 (2013)
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