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"Chip-Level Performance Maximization Using ASIS (Application-Specific ..."

Noriaki Oda et al. (2007)

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DOI: 10.1093/IETELE/E90-C.4.848

access: closed

type: Journal Article

metadata version: 2020-10-26

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  - https://dblp.org/rec/journals/ieicet/OdaIKTKSOYKSHU07
Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno:
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. IEICE Trans. Electron. 90-C(4): 848-855 (2007)

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