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"A 128-bit Chip Identification Generating Scheme Exploiting Load ..."

Shunsuke Okumura et al. (2012)

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DOI: 10.1587/TRANSFUN.E95.A.2226

access: closed

type: Journal Article

metadata version: 2024-03-11

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  - journals/ieicet/OkumuraYKY12
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/OkumuraYKY12
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2226-2233 (2012)

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