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"A 66-333-MHz 12-mW register-controlled DLL with a single delay line and ..."

Young-Jin Jeon et al. (2004)

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DOI: 10.1109/JSSC.2004.835809

access: closed

type: Journal Article

metadata version: 2022-04-22

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Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo-Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong-June Park:
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. IEEE J. Solid State Circuits 39(11): 2087-2092 (2004)

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